Ferroelectric Gate Capacitor Layout for Overlap Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit devices become denser, the increasing overlap capacitance between components degrades AC performance and requires reduced capacitance for low power consumption, which existing technologies have not effectively addressed.
Innovation Solution
Incorporating both a positive capacitor and a ferroelectric or negative capacitor in semiconductor devices, such as MOSFETs, where the ferroelectric or negative capacitor is electrically connected to the gate electrode and source/drain electrodes, allowing for tuning of threshold voltage and other characteristics, and reducing overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density in integrated circuit is increased, then productivity is improved, but overlap capacitance between components increases degrading AC performance
Solution Approach 1:
A ferroelectric capacitor is introduced as an intermediary component between the gate electrode and the channel. This ferroelectric capacitor couples with the gate to provide negative capacitance effect, which compensates for the harmful overlap capacitance introduced by high device density, thereby maintaining AC performance while enabling higher productivity
Solution Approach 2:
The invention changes the electrical parameters of the gate by introducing a ferroelectric material with specific polarization characteristics. The ferroelectric capacitor's unique charge-discharge behavior modifies the effective gate capacitance, reducing the impact of overlap capacitance and enabling continued performance scaling with increased device density
2Productivity
If device density is increased, then productivity is improved, but power consumption increases due to increased capacitance
Solution Approach 1:
The ferroelectric capacitor serves as an energy-managing intermediary that reduces the effective capacitance seen by the gate driver. By utilizing the ferroelectric material's ability to maintain polarization states with minimal energy, the system reduces dynamic power consumption while supporting higher device density
Solution Approach 2:
The invention changes the capacitance parameter of the gate structure by incorporating ferroelectric material, which exhibits non-linear capacitance characteristics. This parameter change reduces the effective overlap capacitance, thereby reducing power consumption proportional to C*V^2*f while maintaining device density
3Adaptability or versatility
If threshold voltage is tuned using ferroelectric capacitor, then adaptability is improved, but device complexity increases
Solution Approach 1:
The ferroelectric capacitor structure is designed to serve multiple functions: it provides threshold voltage tuning, compensates for overlap capacitance, and enables negative capacitance operation. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity while improving adaptability
Solution Approach 2:
The invention merges the threshold voltage control function with the overlap capacitance compensation function into a single ferroelectric capacitor component. By combining these functions, the device achieves enhanced adaptability without proportionally increasing complexity, as one component performs multiple critical roles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves device performance by reducing overlap capacitance, achieving subthreshold swing of less than 60 mV/dec at 300K and enabling both memory and logic device applications.
Implementation Method 1
a ferroelectric or negative capacitor formed on the substrate
Implementation Method 2
a ferroelectric or negative capacitor formed on the substrate
Implementation Method 3
achieving subthreshold swing of less than 60 mV/dec at 300K
Data Source
AI summary
A semiconductor device having a ferroelectric/negative capacitor and a method of manufacturing the same, and an electronic device including the semiconductor device are provided. According to the embodiments, the semiconductor device may include: a gate electrode and a source/drain electrode formed on a substrate; a positive capacitor formed on the substrate, a first terminal of the positive capacitor being electrically connected to the gate electrode; a ferroelectric or negative capacitor formed on the substrate, a first terminal of the ferroelectric or negative capacitor being electrically connected to the gate electrode, wherein a second terminal of one of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to a gate voltage application terminal, and a second terminal of the other of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to the source/drain electrode.