Ferroelectric Transistor Gate Stack With Core-Shell Nanoparticles
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Solution Overview
Problem
The downsizing of semiconductor devices, particularly dynamic random-access memory (DRAM) devices, faces challenges in increasing integration density and reducing leakage currents due to the complexity of capacitor formation, limiting the application of low-power operations in these devices.
Innovation Solution
A semiconductor device design incorporating ferroelectric transistors with a base dielectric layer and nanoparticles having a core-shell structure, where the nanoparticles are dispersed in the dielectric layer, enhancing the ferroelectric material's crystallization and stress, thereby improving the transistor's reliability and memory window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of capacitor increases to improve integration density, then the degree of integration increases, but the difficulty level of capacitor forming process increases and leakage current occurs
Solution Approach 1:
The patent changes the material parameters of the gate insulating layer by incorporating nanoparticles with core-shell structure into the base dielectric layer. This material parameter change enables the gate insulating layer to maintain insulation performance while being formed through a simplified process, resolving the contradiction between integration density improvement and process complexity increase.
Solution Approach 2:
The patent uses composite materials by combining base dielectric layer with nanoparticles having core-shell structure to form the gate insulating layer. This composite structure provides both the insulation properties needed for high integration density and the structural stability to simplify the forming process, thereby resolving the technical contradiction.
2Reliability
If the thickness of ferroelectric layer increases to improve memory window, then the ferroelectric characteristics are maintained, but crystal grain size control becomes difficult
Solution Approach 1:
The patent applies local quality by creating nanoparticles with core-shell structure where the core and shell have different materials and properties. The core provides crystal grain nucleation sites while the shell controls grain growth, enabling precise crystal grain size control even when the ferroelectric layer thickness is increased to maintain ferroelectric characteristics.
Solution Approach 2:
The nanoparticles with core-shell structure act as intermediaries between the base dielectric layer and the crystal grain formation. They mediate the crystal grain growth process by providing controlled nucleation sites, thereby enabling precise control of crystal grain size while maintaining ferroelectric characteristics in thicker layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases the reliability of ferroelectric transistors by reducing crystal grain size and maintaining ferroelectric characteristics even at increased thickness, enabling improved integration density and low-power operation in semiconductor devices.
Implementation Method 1
enhancing the ferroelectric material's crystallization and stress
Data Source
AI summary
A semiconductor device includes bit lines arranged on a substrate and extending in a first horizontal direction; channel layers respectively arranged on the plurality of bit lines; word lines respectively arranged on the plurality of channel layers, and extending in a second horizontal direction; and ferroelectric layers arranged between the plurality of channel layers and the plurality of word lines, wherein the plurality of ferroelectric layers comprise a base dielectric layer and a nanoparticle, the nanoparticle dispersed and arranged in the base dielectric layer, respectively, the nanoparticle has a core-shell structure including a core and a shell.