Ferroelectric Gate Dielectric in 3D Nonvolatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile memory devices face challenges in ensuring structural stability and operational reliability, particularly as design rules shrink and integration increases, with existing three-dimensional structures not adequately addressing these needs.
Innovation Solution
A method of manufacturing a nonvolatile memory device involving a stacked structure with interlayer insulating and sacrificial layers, where a ferroelectric material layer is used as a gate dielectric, and a vertical gate electrode configuration is employed, with a conductive channel layer and gate electrode layers to enhance ferroelectric characteristics through heat treatment and capping layer functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional structure is adopted to increase integration, then device capacity increases, but structural stability deteriorates
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical structures by stacking multiple interlayer insulating layers and sacrificial layers alternately, then forming gate electrode layers and channel layers vertically. This dimensional change enables increased storage capacity while maintaining structural integrity through the carefully designed alternating layer configuration.
2Quantity of substance
If design rules are reduced to increase integration, then device capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into multiple discrete alternating layers including interlayer insulating layers and sacrificial layers, each with specific thicknesses and material compositions. This segmentation allows for precise control of each layer during manufacturing, enabling reduced design rules while maintaining achievable manufacturing precision through sequential deposition and processing of individual layers.
3Reliability
If ferroelectric material layer is used as gate dielectric, then nonvolatile storage capability improves, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates the ferroelectric material layer as the gate dielectric during the initial formation of the alternating stacked structure, before subsequent gate electrode and channel layer formation. This preliminary action ensures the ferroelectric layer is properly positioned and integrated early in the manufacturing process, enabling nonvolatile storage capability while managing overall manufacturing complexity through systematic process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a reliable nonvolatile memory device with improved ferroelectric characteristics, enabling effective storage of multiple electric signals in a three-dimensional structure, ensuring structural and functional reliability.
Implementation Method 1
a dielectric structure, and a channel layer that are formed on a side wall of the first trench, the dielectric structure including a ferroelectric layer
Implementation Method 2
enabling effective storage of multiple electric signals in a three-dimensional structure, ensuring structural and functional reliability
Data Source
AI summary
Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. The stacked structure includes at least one interlayer insulating layer and at least one sacrificial layer alternately stacked with the at least one interlayer insulating layer. A first trench is formed to extend through the stacked structure and to expose the conductive substrate structure. A first gate electrode layer, a dielectric structure, and a channel layer are formed on a side wall of the first trench, the dielectric structure including a ferroelectric layer. At least one recess is formed to expose a side wall of the first gate electrode layer by removing the at least one sacrificial layer. At least one second gate electrode layer is formed by filling the at least one recess with a conductive layer.