Ferroelectric Gate Insulating Film for Threshold Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in controlling threshold voltage and reducing erroneous writing due to the limitations of existing gate insulating films, particularly in the distribution and concentration of additive elements within the ferroelectric films, which affect the ferroelectricity and reliability of memory cells.
Innovation Solution
The semiconductor memory device incorporates a gate insulating film with a ferroelectric film having specific additive regions and a memory region, where the concentration and distribution of elements like ruthenium, titanium, molybdenum, tantalum, tungsten, and platinum are carefully managed to control the crystal structure and ferroelectricity, reducing electron trapping and improving threshold voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate insulating film is used, then the manufacturing process is simple, but the threshold voltage control is poor and erroneous writing occurs
Solution Approach 1:
The gate insulating film is segmented into multiple functional layers: a first insulating film containing additive elements (Ru, Ti, Mo, Ta, W, or Pt) to control crystal structure and prevent erroneous writing, and a second insulating film as a barrier layer. This segmentation allows each layer to perform its specific function optimally, improving threshold voltage control while managing the complexity through functional division.
Solution Approach 2:
Additive elements are locally concentrated in the first insulating film at specific positions (closer to the ferroelectric film interface) with controlled concentrations (0.1-10 at%). This local quality enhancement ensures that the crystal structure control and erroneous writing prevention occur precisely where needed, without requiring uniform distribution throughout the entire gate insulating film structure.
2Reliability
If additive elements are uniformly distributed in the gate insulating film, then the manufacturing is easier, but the ferroelectricity and crystal structure control are insufficient
Solution Approach 1:
The additive elements are distributed non-uniformly with higher concentration (0.1-10 at%) in the first insulating film, particularly near the interface with the ferroelectric film, rather than uniform distribution. This local quality approach enables effective crystal structure control and ferroelectricity enhancement in the critical region without requiring precise uniform distribution throughout the entire film thickness.
Solution Approach 2:
The concentration of additive elements is optimized within specific ranges (0.1-10 at%) to achieve the desired crystal structure and ferroelectric properties. By controlling the concentration parameter within this range, the patent achieves reliable ferroelectricity control while maintaining manufacturability through established deposition techniques.
3Reliability
If the concentration of additive elements is high, then the crystal structure control is better, but the manufacturing precision becomes more difficult to control
Solution Approach 1:
The additive element concentration is optimized within the range of 0.1-10 at%, which provides sufficient crystal structure control and erroneous writing prevention while remaining achievable with conventional manufacturing techniques. This parameter range balances the need for effective ferroelectricity control with the practical constraints of manufacturing precision.
Solution Approach 2:
Rather than requiring high concentrations throughout the entire gate insulating film, the additive elements are concentrated locally in the first insulating film (0.1-10 at%). This local concentration approach achieves effective crystal structure control in the critical interface region while keeping the overall manufacturing precision requirements manageable.
4Reliability
If no barrier layer is provided, then the device complexity is reduced, but electron trapping increases and reliability decreases
Solution Approach 1:
The gate insulating film is divided into a first insulating film (containing additive elements for crystal structure control) and a second insulating film (barrier layer to prevent electron trapping). This segmentation assigns specific functions to each layer, with the second insulating film specifically addressing electron trapping and erroneous writing prevention, thereby improving reliability through functional specialization.
Solution Approach 2:
The second insulating film acts as an intermediary barrier layer between the first insulating film and the ferroelectric film. This intermediate layer prevents direct electron trapping at the interface while maintaining the beneficial crystal structure control provided by the additive elements in the first insulating film, thus reducing erroneous writing without requiring the additive elements to directly contact the ferroelectric film.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of memory cells by reducing erroneous writing and improving the control of threshold voltage, leading to better performance and longevity of the semiconductor memory device.
Implementation Method 1
a first insulating film provided between the semiconductor layer and the gate electrode, and including at least one of oxygen (O), hafnium (Hf), or a first additive element, the first insulating film formed with an orthorhombic crystal structure
Data Source
AI summary
A semiconductor memory device includes a semiconductor layer; a gate electrode; a first insulating film provided between the semiconductor layer and the gate electrode, and including at least one of oxygen, hafnium, or a first additive element; and a second insulating film provided between the first insulating film and the gate electrode. The first insulating film includes a first additive region, a second additive region provided between the first additive region and the gate electrode, and a memory region provided between the first additive region and the second additive region. The first additive region includes a second additive element selected from a group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof. The second additive region includes a third additive element selected group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof.