Ferroelectric Gate Insulator Layout for Stable 3D NAND Memory Cells
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Solution Overview
Problem
Existing three-dimensional NAND flash memory devices face instability in operation when memory cells are scaled down, due to fluctuations in current and threshold voltage caused by the polarization state of ferroelectric materials in the gate insulating layer, leading to unreliable data storage and retrieval.
Innovation Solution
A semiconductor memory device with a gate insulating layer containing hafnium and zirconium oxides in an orthorhombic or trigonal crystal system, where the distance between the second region and the semiconductor layer is larger than between the first region and the semiconductor layer, and a conductive layer is introduced between the gate insulating layer and the interface insulating layer to stabilize the current and reduce the influence of polarization states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate insulating layer is thinned to scale down the memory cell, then the hole diameter is reduced and integration is increased, but the operation stability deteriorates due to current fluctuations and threshold voltage variations
Solution Approach 1:
The gate insulating layer is divided into two regions with different thicknesses: a first region closer to the semiconductor layer and a second region farther away. The first region has a smaller thickness to enable scaling, while the second region has a larger thickness to maintain stability. This local differentiation allows simultaneous achievement of small memory cell size and stable operation.
Solution Approach 2:
A conductive layer is introduced between the gate insulating layer and the interface insulating layer. This conductive layer acts as an intermediary that stabilizes the electric field distribution and reduces the influence of polarization state fluctuations, thereby improving operation stability while maintaining the thinned gate insulating layer structure.
2Reliability
If a uniform thick gate insulating layer is used, then operation stability is maintained, but the memory cell size increases and integration density decreases
Solution Approach 1:
Instead of using a uniform thick gate insulating layer, the invention applies local quality differentiation by creating two regions with different thicknesses. The first region near the semiconductor layer is thinner to reduce overall cell size, while the second region is thicker to maintain the stability benefits of a thicker insulator.
Solution Approach 2:
The invention transitions from a one-dimensional uniform thickness approach to a two-dimensional thickness distribution approach. By varying the thickness in the vertical dimension across different horizontal regions, the design achieves both size reduction and stability maintenance simultaneously.
3Ease of manufacture
If the gate insulating layer is thinned uniformly, then manufacturing complexity is reduced, but operation stability deteriorates due to increased polarization state influence
Solution Approach 1:
The gate insulating layer is structured with local quality variation, having different thicknesses in different regions. This can be implemented through selective etching or deposition processes that are well-established in semiconductor manufacturing, making the dual-thickness structure achievable without excessive manufacturing complexity.
Solution Approach 2:
The gate insulating layer is segmented into two distinct regions with different thickness characteristics. This segmentation allows each region to be optimized for its specific function while using standard fabrication techniques to create the differentiated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution stabilizes the current flowing through the memory cell, ensuring stable operation and reducing variations in threshold voltage, thereby enhancing the reliability of data storage and retrieval in scaled-down memory devices.
Implementation Method 1
a gate insulating layer containing at least one metal element of hafnium (Hf) and zirconium (Zr) and oxygen (O), the gate insulating layer including a first region between the first gate electrode layer and the semiconductor layer, a second region between the first gate electrode layer and the second gate electrode layer, and a third region between the second gate electrode layer and the semiconductor layer, the gate insulating layer in which the first region has a crystal of an orthorhombic crystal system or a trigonal crystal system as a main constituent substance
Data Source
AI summary
A semiconductor memory device of an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a second gate electrode layer provided apart from the first gate electrode layer in the first direction; and a gate insulating layer containing oxygen and at least one metal element of hafnium or zirconium, the gate insulating layer including a first region between the first gate electrode layer and the semiconductor layer, a second region between the first gate electrode layer and the second gate electrode layer, and a third region between the second gate electrode layer and the semiconductor layer, the first region including a crystal of an orthorhombic crystal system or a trigonal crystal system as a main constituent substance, and a distance between the second region and the semiconductor layer being larger than a distance between the first region and the semiconductor layer.