Semiconductor Integrated Circuit With Ferroelectric Gate Insulator
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Solution Overview
Problem
Conventional semiconductor integrated circuits require separate production processes for field-effect transistors with and without memory holding functions, leading to increased production steps, yield degradation due to material contamination, and larger layout areas, as they use different materials like silicon and ferroelectric materials.
Innovation Solution
A semiconductor integrated circuit design that includes field-effect transistors capable of switching between non-hysteresis and hysteresis operation states, allowing for the same substrate to produce both memory and logical operation transistors using a gate insulating structure with a ferroelectric film, thereby simplifying production and reducing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate production processes are used for field-effect transistors with and without memory holding functions, then the transistors can be produced with specialized materials, but the number of production steps increases and manufacturing complexity increases
Solution Approach 1:
The patent applies universality by designing a single production process that can produce both memory-type transistors (with ferroelectric gate insulating structures) and logic-type transistors (with conventional gate insulating structures) using the same manufacturing steps. The key is that the ferroelectric layer and conventional insulating layer are formed through the same process sequence, allowing either layer to be present depending on the desired transistor type, thereby eliminating the need for separate production lines.
Solution Approach 2:
The patent utilizes parameter changes by controlling the presence or absence of the ferroelectric layer through voltage application during the formation process. By applying specific voltages, the ferroelectric layer can be formed or removed selectively, allowing the same production process to generate different transistor types based on parameter control rather than requiring entirely different manufacturing processes.
2Manufacturing precision
If different materials are used for memory and logic transistors, then each transistor type can be optimized, but material contamination occurs and yield decreases
Solution Approach 1:
The patent applies homogeneity by using the same base materials and production processes for both memory and logic transistors. The gate insulating structures are formed through identical deposition and processing steps, ensuring that no foreign materials are introduced during production. This eliminates contamination risks associated with handling different materials separately while maintaining the ability to produce different transistor types through controlled parameter changes.
3Manufacturing precision
If separate production processes are used for memory and logic transistors, then each transistor type can be optimized, but the layout area increases
Solution Approach 1:
The patent enables dense integration by making the production process universal, allowing memory transistors and logic transistors to be fabricated using the same steps. This eliminates the need for separate fabrication zones and allows for tighter packing of different transistor types on the same substrate, thereby reducing the overall layout area while maintaining optimized performance for each transistor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the production process, improves yield by reducing material contamination issues, and minimizes layout area by enabling the same substrate to produce transistors for both memory and logical operations without separate processes.
Implementation Method 1
a gate insulating structure with a ferroelectric film
Implementation Method 2
capable of assuming a first operation state wherein a voltage-drain current property between the gate conductor and the substrate region exhibits non-hysteresis characteristics or pseudo non-hysteresis characteristics and a second operation state wherein the voltage-drain current property exhibits hysteresis characteristics
Data Source
AI summary
A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.