Ferroelectric Gate Dielectric Layering for Stable Remanent Polarization
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Solution Overview
Problem
Current ferroelectric memory devices face challenges in achieving high remanent polarization stability and uniformity, which affects their ability to effectively store and read logic information due to limitations in the crystallization and diffusion control of ferroelectric materials in gate dielectric layers.
Innovation Solution
A ferroelectric semiconductor device is designed with a substrate having a channel structure, a trench pattern, and alternating ferroelectric and non-ferroelectric layers, where a crystalline diffusion barrier layer contacts the ferroelectric layer and an amorphous insulation pattern contacts the non-ferroelectric layer, enhancing polarization alignment and stability through controlled crystallization and material stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ferroelectric material layer is used in a gate dielectric layer, then nonvolatile storage of logic information is achieved, but remanent polarization stability and uniformity are insufficient
Solution Approach 1:
The gate dielectric layer is segmented into multiple alternating ferroelectric and non-ferroelectric layers. This segmentation allows each ferroelectric layer to contribute to remanent polarization while the non-ferroelectric layers provide isolation and stability, collectively improving both polarization uniformity and stability across the entire gate dielectric structure.
Solution Approach 2:
The gate dielectric layer is constructed as a composite structure combining ferroelectric materials (for polarization) and non-ferroelectric materials (for stability). This composite approach leverages the complementary properties of both material types to achieve enhanced remanent polarization stability and uniformity that neither material could provide alone.
2Manufacturing precision
If crystallization control is improved to enhance polarization alignment, then manufacturing complexity increases
Solution Approach 1:
Different regions of the gate dielectric layer are assigned different material properties: ferroelectric layers in regions requiring polarization alignment and non-ferroelectric layers in regions requiring structural stability. This local differentiation simplifies crystallization control by allowing each layer to be optimized independently for its specific function.
Solution Approach 2:
The alternating layered structure is prepared in advance during manufacturing, with ferroelectric and non-ferroelectric layers pre-positioned before final crystallization treatment. This preliminary arrangement establishes the framework for polarization alignment, reducing the complexity of subsequent crystallization control processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the uniformity and magnitude of ferroelectric polarization, enabling improved storage and reading of signal information by increasing the difference between remanent polarization states, thus enhancing the reliability of ferroelectric semiconductor devices.
Implementation Method 1
the diffusion barrier layer pattern having a crystalline structure contacts the ferroelectric layer pattern
Implementation Method 2
the insulation pattern having an amorphous structure contacts the non-ferroelectric layer pattern
Implementation Method 3
a ferroelectric material refers to a material having spontaneous electrical polarization in a state in which no external electric field is applied
Implementation Method 4
the ferroelectric material can exhibit a polarization hysteresis behavior when an external electric field is applied
Implementation Method 5
Portions of the ferroelectric material layer that contact the ferroelectric crystallization inducing layers, are crystallized to form a ferroelectric layer pattern
Data Source
AI summary
A ferroelectric semiconductor device includes a substrate having a channel structure, a trench pattern having a bottom surface and a sidewall surface in the channel structure, a dielectric layer disposed on the bottom surface and the sidewall surface of the trench pattern, and a gate electrode layer disposed on the dielectric layer. The dielectric layer includes a ferroelectric layer pattern and a non-ferroelectric layer pattern that are disposed along the sidewall surface of the trench pattern.


