Ferroelectric Gate Dielectric Stack for Low-EOT Leakage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down equivalent oxide thickness (EOT) of gate layers, which leads to increased gate leakage current, interface traps, and reduced mobility, affecting device performance and reliability.
Innovation Solution
Incorporating a ferroelectric layer in the gate dielectric stack, coupled with dielectric layers, to enhance the equivalent dielectric constant and reduce EOT, thereby alleviating leakage current issues and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If EOT is scaled down to improve device performance, then device performance is improved, but gate leakage current increases and reliability deteriorates
Solution Approach 1:
The patent employs a composite gate dielectric stack comprising multiple layers with different dielectric constants. The stack includes a first dielectric layer with a first dielectric constant and a second dielectric layer with a second dielectric constant, creating a composite structure that achieves lower effective EOT while maintaining reliability by distributing electrical stress across layers with complementary properties
Solution Approach 2:
The patent changes the dielectric constant parameter across different layers of the gate dielectric stack. By using materials with different dielectric constants (k-values) in different layers, the effective EOT is reduced without proportionally increasing gate leakage, as the high-k layers provide capacitance while low-k layers provide leakage barrier properties
2Productivity
If EOT is scaled down to increase inversion charge, then device performance is improved, but interface traps increase and mobility degrades
Solution Approach 1:
The patent applies local quality by assigning different dielectric constant values to different spatial locations (layers) within the gate dielectric stack. The first dielectric layer and second dielectric layer each have optimized k-values tailored to their specific positions and functional requirements, allowing the interface region to maintain high quality while achieving overall lower EOT
Solution Approach 2:
The composite gate dielectric stack uses materials with different dielectric constants in different layers to simultaneously achieve high inversion charge and maintain interface quality. The layered composite structure allows optimization of each layer's material properties for its specific function while achieving the desired overall electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of ferroelectric layers in the gate dielectric stack increases the dielectric constant, reduces leakage voltage, and allows for the potential of scaling to smaller node technologies while maintaining device reliability.
Implementation Method 1
Incorporating a ferroelectric layer in the gate dielectric stack, coupled with dielectric layers, to enhance the equivalent dielectric constant and reduce EOT
Data Source
AI summary
The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion and the total volume of the first portion is greater than a total volume of the third portion.