Ferroelectric Gate Structure for Low-SS Semiconductor Scaling
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Solution Overview
Problem
Existing silicon-based transistors face limitations in improving operating characteristics and scaling down due to high power density and subthreshold swing (SS) values, which restrict further device miniaturization and power reduction.
Innovation Solution
A semiconductor device incorporating a substrate with a channel layer, a ferroelectric layer, and a fixed charge layer, where the fixed charge layer generates a negative capacitance effect, allowing for voltage amplification and reduced SS values by adjusting the charge density and work function of the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing silicon-based transistors are used, then the device structure is simple and manufacturing is mature, but the subthreshold swing (SS) value is limited to about 60 mV/dec and power density increases with scaling
Solution Approach 1:
The patent employs a composite gate structure consisting of a ferroelectric layer (e.g., HfO2, Pb(Zr,Ti)O3) combined with a high-k dielectric layer. This composite material approach enables the gate to achieve both high capacitance for improved SS and low leakage for reduced power density, overcoming the limitations of conventional silicon-based transistor gates.
Solution Approach 2:
The patent utilizes the ferroelectric phase transition properties by controlling the composition ratio (e.g., Zr/Ti ratio in PZT) and crystal structure (tetragonal, orthorhombic, rhombohedral phases) of the ferroelectric material. By adjusting these parameters, the device achieves optimized SS values below 60 mV/dec and controlled power density characteristics.
2Productivity
If transistor size is reduced for scaling down, then device density increases, but power density increases and operating voltage cannot be lowered below 0.8 V
Solution Approach 1:
The ferroelectric gate structure enables operating voltages below 0.8 V by utilizing the high capacitance of the ferroelectric layer, which amplifies the gate voltage effect. This allows continued device scaling and increased density while maintaining low power density through reduced operating voltage.
3Reliability
If existing silicon-based transistors are used, then manufacturing process is mature, but further improvement in operating characteristics and scaling down is limited
Solution Approach 1:
The patent introduces a multi-layer gate structure with ferroelectric and high-k dielectric layers, replacing the conventional single-layer gate. This composite structure improves operating characteristics (SS value, threshold voltage control) while using established fabrication techniques like atomic layer deposition (ALD) and pulsed laser deposition (PLD), thereby managing device complexity through proven manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables improved performance by lowering SS values below 60 mV/dec, enabling further device scaling and reducing power consumption, thus overcoming the limitations of traditional silicon-based transistors.
Implementation Method 1
The fixed charge layer may have a charge density that generates a negative capacitance effect in response to the channel layer being in an inversion state.
Data Source
AI summary
Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a channel layer at least one of on or in the substrate, an insulation layer on the substrate, a ferroelectric layer on the insulation layer, a fixed charge layer on an interface between the insulation layer and the ferroelectric layer, the fixed charge layer including charges of a first polarity, and a gate on the ferroelectric layer.