Ferroelectric Gate Structure for Low-Voltage MOSFET Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in reducing power density due to high subthreshold swing limitations in silicon-based MOSFETs, making it difficult to achieve low supply voltages necessary for further miniaturization and integration.
Innovation Solution
Incorporating a ferroelectric material layer in the semiconductor device to form a negative capacitance ferroelectric capacitor, which increases overall capacitance and allows for voltage amplification, thereby improving switching speed and reducing subthreshold swing below 60 mV/decade.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-based MOSFET is used, then device reliability is maintained, but subthreshold swing is limited to 60 mV/decade or more, making it difficult to achieve low supply voltage
Solution Approach 1:
The patent employs a composite structure combining silicon-based MOSFET with ferroelectric material layer to create a negative capacitance device. The ferroelectric layer (e.g., hafnium oxide, barium strontium titanium oxide) is integrated with the gate structure, forming a composite system that leverages the stability of silicon technology while introducing ferroelectric properties to achieve subthreshold swing below 60 mV/decade and enable lower supply voltages
Solution Approach 2:
The patent changes the electrical parameters of the gate structure by introducing ferroelectric material with negative capacitance characteristics. This parameter change transforms the gate's voltage amplification capability, allowing the subthreshold swing to be reduced below the conventional 60 mV/decade limit and enabling operation at lower supply voltages while maintaining device reliability
2Productivity
If transistor size is miniaturized to increase integration density, then degree of integration is improved, but power density increases exponentially
Solution Approach 1:
The patent changes the fundamental electrical parameters of the transistor by integrating ferroelectric material in the gate structure. This creates negative capacitance effects that reduce the voltage swing required for switching, thereby reducing power consumption and allowing higher integration densities without exponential increases in power density
Solution Approach 2:
The patent substitutes the conventional thermal emission-based switching mechanism of silicon MOSFETs with a ferroelectric field-effect mechanism. This substitution enables more efficient charge control and reduces the energy required for switching operations, addressing the power density issue associated with miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a ferroelectric capacitor with negative capacitance enhances voltage amplification and improves transistor switching speed, enabling subthreshold swing reduction, thus addressing the limitations of silicon-based MOSFETs and supporting further miniaturization and integration.
Implementation Method 1
the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group
Implementation Method 2
a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.