Ferroelectric Gate NCFET Layout Flexibility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional approaches for scaling down semiconductor devices, such as MOSFETs, face challenges in device density and circuit performance due to restricted design rule limitations, and are not entirely satisfactory in modifying threshold voltage (Vt) and circuit layout flexibility.
Innovation Solution
The use of negative-capacitance field-effect transistors (NCFETs) incorporating ferroelectric materials, which allow for flexible gate widths and lengths, enabling easier integration and more flexible layout designs, along with a manufacturing method involving the formation of fins, dummy gates, ferroelectric layers, and metal gate electrodes, to achieve lower VDD and steep subthreshold swing for reduced standby power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOSFET scaling is used to increase device density, then device density improves, but processing windows and circuit performance deteriorate due to restricted design rule limitations
Solution Approach 1:
The patent changes the gate structure parameters by introducing ferroelectric layers and adjusting gate width/length ratios, enabling threshold voltage modification without relying solely on conventional scaling, thus maintaining circuit performance while achieving higher device density
Solution Approach 2:
The patent uses composite gate structures combining metal layers with ferroelectric materials (e.g., HfO2, Pb(Zr,Ti)O3), creating new functional properties that enable both high density and reliable circuit operation under restricted design rules
2Manufacturing precision
If different work function metals and metal gates are used to modify threshold voltage, then threshold voltage control improves, but layout flexibility and integration ease deteriorate
Solution Approach 1:
The patent introduces adjustable gate width and length parameters that can be dynamically modified to control threshold voltage, replacing fixed metal gate approaches with flexible ferroelectric gate structures that enable both precise Vt control and layout adaptability
Solution Approach 2:
The gate structure is segmented into multiple functional layers (ferroelectric layer, metal gate electrode, dummy gate components) with independently controllable dimensions, allowing threshold voltage adjustment through geometric parameter variation rather than material substitution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables more flexible and efficient semiconductor device layout, allowing for easier modification of Vt and improved circuit performance by utilizing NCFETs with ferroelectric materials, resulting in lower standby power consumption and enhanced integration capabilities.
Implementation Method 1
The use of negative-capacitance field-effect transistors (NCFETs) incorporating ferroelectric materials, which allow for flexible gate widths and lengths, enabling easier integration and more flexible layout designs, along with a manufacturing method involving the formation of fins, dummy gates, ferroelectric layers, and metal gate electrodes, to achieve lower VDD and steep subthreshold swing for reduced standby power
Data Source
AI summary
A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.