Ferroelectric Gate Structure for Low-Voltage Scaled MOSFETs
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric characteristics and reduced operation voltage.
Innovation Solution
Incorporating a ferroelectric pattern between the active patterns and the gate electrode, with a work function metal pattern and electrode pattern, to create a negative capacitance effect, enhancing sub-threshold swing characteristics and reducing operation voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
A ferroelectric pattern is introduced as an intermediary layer between the gate electrode and the active pattern. This ferroelectric layer generates a negative capacitance effect that amplifies the gate voltage, thereby improving the operational properties of the scaled-down MOS-FET without requiring larger device dimensions.
Solution Approach 2:
The work function of the gate electrode is modified by using a multi-layer structure comprising a first work function metal pattern and a second work function metal pattern. This changes the electrical parameters of the gate, enabling better control over the threshold voltage and improving the overall performance of the scaled-down device.
2Area of moving object
If MOS-FETs are scaled down, then pattern size is reduced, but sub-threshold swing characteristics deteriorate
Solution Approach 1:
The ferroelectric pattern serves as a mediator that enhances the sub-threshold swing characteristics through negative capacitance. This allows scaled-down devices to maintain steep sub-threshold swing without compromising the pattern size reduction.
3Area of moving object
If MOS-FETs are scaled down, then device dimensions are reduced, but operation voltage increases
Solution Approach 1:
The ferroelectric pattern acts as a voltage amplifier through the negative capacitance effect. It boosts the effective gate voltage without requiring an increase in the actual applied voltage, thereby enabling scaled-down devices to operate at lower voltages while maintaining adequate drive current.
Solution Approach 2:
By adjusting the work function of the gate electrode through the multi-layer metal structure, the threshold voltage is optimized to enable low-voltage operation in scaled-down devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ferroelectric pattern improves sub-threshold swing characteristics and reduces operation voltage by inducing a negative capacitance effect, thereby enhancing the performance of semiconductor devices.
Implementation Method 1
Incorporating a ferroelectric pattern between the active patterns and the gate electrode, with a work function metal pattern and electrode pattern, to create a negative capacitance effect, enhancing sub-threshold swing characteristics and reducing operation voltage
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.