Ferroelectric Gate Stack With Blocking Layer for Low-Leakage FeRAM

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Solution Overview

Problem

Ferroelectric random-access memory (FeRAM) structures, particularly MFS-FET and MFIS-FET, face issues with interface reactions, high leakage current, retention, and fatigue due to the interaction between ferroelectric materials and semiconductor substrates, which affect the performance and reliability of these memory devices.

Innovation Solution

A semiconductor structure and method for forming an MFMIS FET with a hafnium zirconium oxide-based ferroelectric layer using atomic layer deposition (ALD) to achieve a thinner ferroelectric layer, incorporating a doped hafnium oxide blocking layer and conductive electrodes with tensile stress to stabilize the ferroelectric layer and reduce electron/hole injection, thereby enhancing remnant polarization and crystallinity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a ferroelectric layer is used as gate dielectric in MFS-FET structure, then non-volatility and low power consumption are achieved, but interface reactions between ferroelectric materials and semiconductor substrates occur causing high leakage current and poor retention

Engineering Contradiction:

Improvememory retention and leakage currentVSAvoidinterface reactions

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An insulating layer is introduced as an intermediary between the ferroelectric layer and the semiconductor substrate. This insulating layer acts as a mediator that prevents direct contact and harmful interface reactions while maintaining the electrical functionality of the gate dielectric stack, thereby reducing leakage current and improving retention without sacrificing the non-volatile memory characteristics

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate dielectric is formed as a composite structure combining the ferroelectric layer and the insulating layer. This composite material approach allows the system to benefit from both the ferroelectric properties (non-volatility, low power) and the insulating properties (interface protection, low leakage) of the combined materials

Inventive Principle:

Principle #40Composite materials

2Speed

If the ferroelectric layer thickness is reduced to improve device performance, then switching speed and capacitance are enhanced, but interface reactions and leakage current increase

Engineering Contradiction:

Improveswitching speedVSAvoidinterface reactions and leakage current

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The insulating layer serves as a protective intermediary that enables the use of thinner ferroelectric layers without directly exposing the semiconductor substrate to harmful interface reactions. This mediator allows the ferroelectric layer to be sufficiently thin for fast switching while the insulating layer prevents the associated increase in leakage current and interface degradation

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If MFS-FET structure is used to achieve simple fabrication, then manufacturing complexity is reduced, but interface reactions cause poor device reliability and high leakage

Engineering Contradiction:

Improvefabrication simplicityVSAvoiddevice reliability and leakage current

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The insulating layer is formed as a preliminary protective layer before the ferroelectric layer is deposited. This preliminary action prevents interface reactions from occurring during subsequent processing steps and device operation, ensuring reliable device performance from the outset

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution improves the feasibility and performance of MFMIS memory structures by reducing leakage current, enhancing retention, and stabilizing the ferroelectric layer, leading to improved endurance and reliability of FeRAM devices.

Implementation Method 1

using atomic layer deposition (ALD) to achieve a thinner ferroelectric layer

Methodology Applied

Scientific EffectAtomic layer deposition:

Implementation Method 2

ferroelectric random-access memory (FeRAM)... uses a ferroelectric material as a part of its gate dielectric... enhancing remnant polarization

Methodology Applied

Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS12027601B2Method for forming semiconductor structure

Publication Date: 2024.07.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.