Ferroelectric Gate Stack Structure for Low-Voltage CMOS Switching
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Solution Overview
Problem
The reduction of power density in CMOS transistors is hindered by the limited decrease in drive voltage, as silicon-based MOSFETs face challenges in achieving low supply voltages due to thermal emission properties, leading to increased power consumption in integrated circuits.
Innovation Solution
The use of semiconductor devices with gate insulating films incorporating ferroelectric material films exhibiting negative capacitance characteristics, which are combined with paraelectric material films to enhance overall capacitance and reduce subthreshold swing, thereby decreasing the drive voltage and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If silicon-based MOSFETs are used with thermal emission properties, then the transistor structure is simple and manufacturing is easy, but the drive voltage cannot be reduced significantly leading to increased power density
Solution Approach 1:
The patent changes the electrical parameters of the gate insulating film by introducing ferroelectric materials with negative capacitance characteristics. This alters the capacitance-voltage relationship, enabling sub-60mV/decade subthreshold swing and reducing drive voltage from conventional levels to below 0.5V, directly addressing the power density issue while maintaining manufacturing feasibility
Solution Approach 2:
The patent employs composite gate insulating films combining ferroelectric materials (e.g., HfO2, Pb(Zr,Ti)O3) with paraelectric materials (e.g., SrTiO3, BaTiO3). This composite structure leverages the negative capacitance of ferroelectric phases and the high dielectric constant of paraelectric phases to achieve enhanced capacitance control and reduced drive voltage, solving the contradiction between energy efficiency and operational reliability
2Productivity
If the transistor size is decreased to increase integration density, then the degree of integration increases, but the drive voltage reduction is not significantly improved leading to exponentially increased power density
Solution Approach 1:
The patent changes the fundamental electrical parameters of miniaturized transistors by implementing ferroelectric gate insulating films. This enables the subthreshold swing to drop below 60mV/decade, allowing drive voltage reduction to 0.3-0.5V even at scaled dimensions. This parameter change decouples the relationship between size scaling and power density, enabling high integration without exponential power increase
Solution Approach 2:
The patent applies ferroelectric materials with specific crystal phases (orthorhombic, tetragonal) in the gate insulating film to create localized regions of negative capacitance. This local quality enhancement at the gate interface provides superior electrostatic control for miniaturized transistors, enabling low-power operation at scaled dimensions where conventional materials would fail
3Reliability
If ferroelectric material films with negative capacitance characteristics are used in the gate insulating film, then the subthreshold swing decreases below 60 mV/decade and drive voltage reduces, but the device structure and material composition become more complex
Solution Approach 1:
The patent uses composite structures of ferroelectric and paraelectric materials where the paraelectric layers (SrTiO3, BaTiO3) provide high dielectric constant and the ferroelectric layers (HfO2, Pb(Zr,Ti)O3) provide negative capacitance. This composite approach achieves sub-60mV/decade subthreshold swing while managing the complexity through systematic material selection and layered architecture that can be integrated into existing CMOS processes
Solution Approach 2:
The gate insulating film is segmented into multiple thin layers of alternating ferroelectric and paraelectric materials. This segmentation allows each layer to be optimized independently for its specific function (negative capacitance or high dielectric constant) while collectively achieving the desired subthreshold swing characteristic. The segmented structure also facilitates manufacturing by enabling sequential deposition of different material systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a subthreshold swing of less than 60 mV/decade at room temperature, reducing the drive voltage and improving the reliability and efficiency of transistors by leveraging the increased capacitance from the series connection of ferroelectric and paraelectric materials.
Implementation Method 1
gate insulating films incorporating ferroelectric material films exhibiting negative capacitance characteristics
Implementation Method 2
leveraging the increased capacitance from the series connection of ferroelectric and paraelectric materials
Data Source
AI summary
A semiconductor device includes a substrate including a first region and a second region, a first gate stack on the first region and including a first gate stacked insulating film and a first gate electrode on the first gate stacked insulating film, and a second gate stack on the second region and including a second gate stacked insulating film and a second gate electrode on the second gate stacked insulating film, wherein a width of the first gate stack is greater than a width of the second gate stack and the second gate stacked insulating film includes a plurality of ferroelectric material films.