Ferroelectric Memory Gate Stack for Interface Defect Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric field effect transistors (FETs) face performance issues due to defect formation at the interfaces between the ferroelectric material and the channel region, as well as between the ferroelectric material and the gate terminal, which affects the threshold voltage and channel resistance.
Innovation Solution
The implementation of a ferroelectric memory device with a bottom gate configuration, where a ferroelectric layer is sandwiched between the gate electrode and the channel layer, and the use of blocking layers made of oxide ferroelectric materials, such as hafnium oxide, to enhance conduction and valence band offsets, thereby reducing leakage current and passivating interfacial trap states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ferroelectric layer is placed between the gate terminal and channel region, then non-volatile memory storage is achieved, but interface defects form between the ferroelectric material and channel region/gate terminal
Solution Approach 1:
An oxide layer is introduced as an intermediary between the ferroelectric layer and the channel region, and another oxide layer is placed between the ferroelectric layer and the gate terminal. These intermediary oxide layers prevent direct contact between the ferroelectric material and the silicon-based structures, thereby eliminating interface defect formation while preserving the non-volatile memory storage capability of the ferroelectric layer.
2Reliability
If blocking layers are added to reduce leakage current, then on-current to off-current ratio improves, but device structure complexity increases
Solution Approach 1:
The oxide layers serve multiple functions simultaneously: they act as blocking layers to reduce leakage current, as interface passivation layers to reduce trap states, and as part of the overall device architecture. By combining multiple functions into a single structural element, the patent improves the Ion/Ioff ratio without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance of the ferroelectric FET by reducing leakage current, enhancing the ratio of on-current to off-current (Ion/Ioff), and improving field effect mobility, while also reducing negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI).
Implementation Method 1
a ferroelectric layer 106...configured to store binary data as polarizations with different polarities by adjusting an electric field across the ferroelectric layer 106
Implementation Method 2
blocking layers 114, 116...enhance conduction and valence band offsets, thereby reducing leakage current
Implementation Method 3
passivating interfacial trap states
Data Source
AI summary
A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.