Ferroelectric Gate Stack Structure for Low-Leakage Steep-Slope Transistors

The patent changes the material parameter of the dielectric layer from conventional silicon oxide to a ferroelectric material (such as hafnium zirconium oxide with specific composition ratios). This material parameter change enables the transistor to achieve sub-threshold swing values less than 60 mV/dec, allowing operation voltage to be reduced to 0.8 V or less while maintaining reliability, thus resolving the contradiction between scaling and operational characteristics.

The patent employs a composite dielectric structure comprising a ferroelectric layer (e.g., HfZrO4) combined with other dielectric materials. This composite approach allows optimization of both electrical characteristics (achieving SS < 60 mV/dec) and physical properties (maintaining stability at scaled dimensions), enabling simultaneous improvement of scaling and operational characteristics.

The patent segments the dielectric structure into multiple distinct layers: a first dielectric layer in contact with the substrate, a ferroelectric crystallization layer above it, and a second dielectric layer capping the ferroelectric layer. This segmentation confines the crystallization process to the ferroelectric layer while preventing it from spreading to the substrate, thus enhancing operational characteristics without causing current leakage.

The patent introduces intermediate dielectric layers (first and second dielectric layers) that act as mediators between the substrate and the ferroelectric crystallization layer. These intermediary layers serve as barriers that prevent crystallization spread and potential current leakage paths, while allowing the ferroelectric layer to maintain its enhanced operational characteristics.