Ferroelectric Gate Dielectric Stack for Low-Power NCFET Scaling

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Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, they face challenges in integrating more components while maintaining performance and efficiency, particularly in achieving high integration density and low standby power consumption.

Innovation Solution

The development of negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices that utilize a gate dielectric stack comprising a ferroelectric layer combined with non-ferroelectric layers, allowing for adjustable negative capacitance to enhance transistor performance by increasing capacitance and improving subthreshold slope.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional transistor scaling is continued to increase integration density, then more components can be integrated into a given area, but standby power consumption increases and performance deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidstandby power consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the electrical parameters of the gate dielectric by introducing a ferroelectric layer with negative capacitance. This alters the capacitance-voltage characteristics of the transistor, enabling steeper subthreshold slopes and lower off-state currents, thereby reducing standby power consumption while maintaining high integration density

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite gate dielectric structure combining ferroelectric material (e.g., HfO2) with non-ferroelectric dielectric layers. This composite structure achieves both high capacitance for performance and low leakage for reduced standby power, resolving the contradiction between integration density and power consumption

Inventive Principle:
Principle #40Composite materials

2Productivity

If feature size is reduced to increase integration density, then more components fit in a given area, but manufacturing precision and device performance become difficult to maintain

Engineering Contradiction:
Improveintegration densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent utilizes the unique parameter of negative capacitance in ferroelectric materials to achieve steeper subthreshold slopes without further scaling. This allows maintaining device performance metrics (such as on-off ratio and drive current) at smaller feature sizes, effectively decoupling performance from feature size scaling

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The ferroelectric layer introduces dynamic switching behavior with hysteresis, enabling the transistor to maintain stable performance characteristics across process variations and temperature changes. This dynamic property compensates for manufacturing variability inherent in scaled devices

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of transistors with improved performance and reduced standby power consumption, enabling higher integration density and efficient operation in integrated circuits.

Implementation Method 1

The ferroelectric layer provides a layer having a negative capacitance Cfe that when combined with the capacitance of the other dielectric layers provides a high capacitance of the combined dielectric stack

Methodology Applied
Scientific EffectNegative capacitance:

Implementation Method 2

a ferroelectric gate dielectric layer (91) formed over the channel regions (58)

Methodology Applied
Scientific EffectFerroelectricity:

Data Source

PatentUS12136659B2Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices
Publication Date: 2024.11.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12136659B2 patent drawing
  • US12136659B2 patent drawing
  • US12136659B2 patent drawing

AI summary

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.