Ferroelectric Gate Stack for Low-Voltage Negative Capacitance FETs
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing the subthreshold swing, which limits their performance and power efficiency, particularly in low power operation, due to the use of high-k gate dielectric materials that do not exhibit negative-capacitance effects.
Innovation Solution
The integration of a ferroelectric layer with a stabilized crystalline phase, such as metastable orthorhombic HfO2, into negative capacitance field effect transistors (NCFETs) to achieve a negative capacitance effect, which is achieved through specific combinations of strain and composition, and manufacturing processes like atomic layer deposition and annealing to form nanocrystals or columnar-shaped crystals within an amorphous matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high-k gate dielectric materials are used, then gate capacitance is increased, but subthreshold swing cannot be reduced below conventional limits
Solution Approach 1:
The patent employs a composite gate stack structure consisting of a high-k dielectric layer combined with a ferroelectric layer. This composite structure enables the system to achieve both high gate capacitance for power efficiency and negative capacitance effect for improved subthreshold swing control. The high-k dielectric provides the necessary capacitance while the ferroelectric layer introduces the negative capacitance effect that steepens the subthreshold characteristic.
Solution Approach 2:
The patent utilizes the phase transition properties of ferroelectric materials to change the electrical parameters of the gate stack. By inducing a phase transition in the ferroelectric layer through applied voltage, the system achieves a negative capacitance state that fundamentally alters the subthreshold swing characteristic, enabling ultra-low power operation without sacrificing reliability.
2Reliability
If ferroelectric material is integrated to achieve negative capacitance effect, then subthreshold swing is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates the ferroelectric layer during the initial gate stack formation process, before subsequent device fabrication steps. The ferroelectric material is deposited and processed early in the manufacturing sequence, allowing its complex properties to be established beforehand. This preliminary action simplifies later processing steps and reduces overall manufacturing complexity despite the inherent complexity of working with ferroelectric materials.
Solution Approach 2:
The gate stack structure designed in the patent serves multiple functions: it provides gate capacitance, enables negative capacitance effect, and maintains compatibility with standard semiconductor fabrication processes. The ferroelectric layer is integrated in a way that allows it to perform its specialized function while the overall structure remains compatible with conventional manufacturing workflows, reducing the increase in device complexity.
3Power
If stabilized crystalline phase ferroelectric layer is formed, then negative capacitance effect is achieved, but process temperature requirements increase
Solution Approach 1:
The patent applies local quality by creating a gradient in the ferroelectric layer structure, with different regions having different crystalline phases or compositions optimized for their specific functions. The stabilized crystalline phase is formed in regions where high-temperature processing is acceptable, while other regions maintain lower-temperature characteristics. This local differentiation allows the system to achieve negative capacitance effect without requiring uniformly high temperatures across the entire device structure.
Solution Approach 2:
The patent uses a composite gate dielectric structure where a high-k dielectric layer is combined with a ferroelectric layer. The high-k dielectric component can be processed at lower temperatures, compensating for the higher temperature requirements of forming the stabilized crystalline phase in the ferroelectric layer. This composite approach allows the system to achieve the desired operational power reduction without subjecting the entire device to excessively high processing temperatures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly lowers the subthreshold swing, enabling steep switching characteristics and reducing power supply voltage, thereby enhancing the operational efficiency of NCFETs for low power applications.
Implementation Method 1
a negative capacitance field effect transistor (NCFET) using a ferroelectric material has been proposed
Implementation Method 2
The integration of a ferroelectric layer with a stabilized crystalline phase, such as metastable orthorhombic HfO2, into negative capacitance field effect transistors (NCFETs) to achieve a negative capacitance effect
Implementation Method 3
manufacturing processes like atomic layer deposition and annealing to form nanocrystals or columnar-shaped crystals within an amorphous matrix
Implementation Method 4
manufacturing processes like atomic layer deposition and annealing to form nanocrystals or columnar-shaped crystals within an amorphous matrix
Data Source
AI summary
In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.