Ferroelectric Gate Stack for Subthreshold Swing Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges with subthreshold swing limitations in MOS FETs, leading to increased power consumption and leakage currents due to the physical limit of 60 mV/decade, which hinders further miniaturization and performance improvement.
Innovation Solution
The method involves forming a ferroelectric layer and a compressive stress layer in a recess of a semiconductor device, followed by a thermal treatment to induce a phase with negative capacitance characteristics, and subsequent removal of the compressive layer to facilitate the deposition of work function and low resistance metal layers, enhancing the device's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a MOS FET device is used with conventional structure, then the manufacturing process is simple, but the subthreshold swing cannot be less than 60 mV/decade due to physical limit, leading to increased power consumption and leakage currents
Solution Approach 1:
The patent introduces a ferroelectric layer in the gate structure that changes the electrical parameters of the device by providing negative capacitance, which amplifies the gate voltage effect and reduces the subthreshold swing below the conventional 60 mV/decade limit, thereby reducing leakage current and power consumption
Solution Approach 2:
The patent uses a composite gate structure consisting of multiple layers including a ferroelectric layer (e.g., HfZrO4), a compressive layer (e.g., TiN), and a work function metal layer, combining materials with different properties to achieve both low subthreshold swing and manufacturability
2Loss of energy
If the gate structure is modified to reduce subthreshold swing, then power consumption is reduced, but the device structure becomes more complex
Solution Approach 1:
The gate structure is segmented into distinct functional layers: a ferroelectric layer for negative capacitance, a compressive layer for stress control, and a work function metal layer for voltage tuning, allowing each layer to be optimized independently while working together to reduce power consumption
Solution Approach 2:
The compressive layer acts as an intermediary between the ferroelectric layer and the work function metal layer, providing mechanical stress to stabilize the ferroelectric phase while allowing the work function metal to be deposited without damaging the underlying ferroelectric structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves subthreshold swing and reduces current leakage, enabling more efficient power management and potentially smaller feature sizes in semiconductor devices.
Implementation Method 1
performing a thermal treatment process to induce a phase with negative capacitance characteristics
Implementation Method 2
forming a compressive layer on the FE layer
Data Source
AI summary
A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.