Ferroelectric Gate Stack Structure to Block Oxide Penetration
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Solution Overview
Problem
Ferroelectric memory devices face challenges in enhancing remanent polarization and memory window due to limitations in the gate insulation layer's ability to maintain hysteresis characteristics and prevent oxide penetration, affecting endurance and performance.
Innovation Solution
A ferroelectric memory device design incorporating a gate insulation layer with a ferroelectric inductive layer and a ferroelectric stack structure, featuring a two-dimensional transition metal dichalcogenide layer and a non-ferroelectric layer, stacked in alternating order, which includes materials like hafnium oxide and zirconium oxide to enhance remanent polarization and memory window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate insulation layer with ferroelectric inductive layer is used, then remanent polarization is enhanced, but oxide penetration at the interface occurs which reduces reliability
Solution Approach 1:
A non-ferroelectric layer is introduced as an intermediary barrier between the ferroelectric inductive layer and the channel layer. This non-ferroelectric layer specifically blocks oxide penetration from the ferroelectric layer to the channel layer, while allowing the ferroelectric layer to maintain its remanent polarization function. The intermediary layer thus resolves the contradiction by preventing harmful oxide diffusion without compromising the desired polarization enhancement.
2Reliability
If ferroelectric material is applied as gate insulation layer, then memory window is increased, but oxide penetration at interface affects performance
Solution Approach 1:
The non-ferroelectric layer serves as a protective intermediary that prevents oxide penetration from the ferroelectric gate insulation layer to the channel layer. This mediator maintains the performance benefits of the ferroelectric material (increased memory window) while eliminating its harmful effect (oxide penetration).
Solution Approach 2:
The gate insulation structure is designed as a composite material system combining ferroelectric and non-ferroelectric layers. The ferroelectric layer provides the desired memory window enhancement, while the non-ferroelectric layer provides oxide barrier functionality. This composite structure resolves the contradiction by integrating materials with complementary properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design significantly enhances remanent polarization and memory window, improving the endurance and performance of ferroelectric memory devices by preventing oxide penetration and maintaining hysteresis characteristics.
Implementation Method 1
Ferroelectric materials or ferroelectrics are materials having ferroelectricity, and maintain self-polarization as internal electric dipole moments are aligned even when an electric field is applied thereto from the outside. In ferroelectric materials, when an external electric field is applied thereto, electric polarization may exhibit a hysteresis characteristic.
Implementation Method 2
The introduction of a gate insulation layer comprising a ferroelectric inductive layer and a ferroelectric stack structure formed on the ferroelectric inductive layer, where the stack is alternately layered with a non-ferroelectric layer, including 2D transition metal dichalcogenides or hafnium/zirconium oxides, to minimize oxide penetration
Data Source
AI summary
A ferroelectric memory device includes a channel layer, a gate insulation layer on the channel layer, and a gate electrode layer on the gate insulation layer. The gate insulation layer includes a ferroelectric inductive layer and a ferroelectric stack structure on the ferroelectric inductive layer, and the ferroelectric stack structure is stacked in an order or reverse order of a ferroelectric layer and a non-ferroelectric layer.