Ferroelectric Gate Stack Treatment for Metal Oxide Suppression
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Solution Overview
Problem
The integration of ferroelectric materials in transistors is hindered by the unintentional formation of a metal oxide layer on the metal gate electrode, which depolarizes the ferroelectric material and compromises electrical performance due to oxygen diffusion during annealing processes, limiting the reduction of subthreshold voltage swing and power consumption in MOSFETs.
Innovation Solution
Implementing a metal-halide gas treatment to remove the metal oxide layer formed on the metal gate layer prior to post metallization annealing, either in-situ or by forming a silicon-based capping layer to prevent oxidation, ensuring the ferroelectric material remains unpolarized and maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate layer is deposited on a ferroelectric layer, then the transistor structure is formed, but a metal oxide layer unintentionally forms on the metal gate electrode during annealing, which depolarizes the ferroelectric material and compromises electrical performance
Solution Approach 1:
A capping layer is introduced as an intermediary between the metal gate layer and the annealing environment. This capping layer prevents oxygen from reaching and oxidizing the metal gate electrode during annealing processes, thereby eliminating the harmful metal oxide layer formation while allowing the annealing to proceed for other process benefits
Solution Approach 2:
The capping layer is deposited on the metal gate layer before the annealing process occurs. This preliminary protective action ensures that when annealing takes place, the metal gate electrode is already shielded from oxygen exposure, preventing oxide formation before it can compromise the ferroelectric material's polarization
2Power
If MOSFET scaling is implemented to increase performance, then speed and power consumption improve, but the subthreshold voltage swing is limited to an ideal value of 60 mV/decade, making it challenging to obtain additional drive voltage and power benefits
Solution Approach 1:
The invention changes the fundamental electrical parameters of the transistor by replacing the conventional MOSFET structure with a ferroelectric field-effect transistor (FeFET) structure. The ferroelectric material in the gate stack enables subthreshold voltage swing to exceed the ideal 60 mV/decade limit, achieving values such as 80-100 mV/decade or higher, which provides additional drive voltage and power benefits beyond what scaling alone can achieve
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the subthreshold voltage swing below 60 mV/decade, allowing for lower operating voltages, reduced power consumption, improved battery life, and decreased heat generation in transistors, while maintaining the on-state to off-state current ratio.
Implementation Method 1
exposing the metal gate layer to a metal-halide gas to remove a metal oxide layer formed on the metal gate layer
Implementation Method 2
forming a silicon-based capping layer to prevent oxidation
Implementation Method 3
performing a post metallization annealing to crystallize the ferroelectric layer
Data Source
AI summary
The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.