Ferroelectric Gate Stack With Crystallization Barrier for Low-Voltage Scaling

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Solution Overview

Problem

Silicon-based electronic devices face limitations in operational characteristics and scaling down due to sub-threshold swing limitations and increased power density, making it difficult to decrease operation voltage below 0.8 V as transistor size decreases.

Innovation Solution

The use of a ferroelectric crystallization layer with a dielectric material having ferroelectricity or anti-ferroelectricity, sandwiched between a gate electrode and a substrate, with a crystallization prevention layer to prevent crystallization spread, and additional layers like high dielectric and high band gap layers to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the size of the logic transistor is decreased to improve scaling, then the operational characteristics improve, but the sub-threshold swing is limited to about 60 mV/dec and operation voltage cannot be decreased below 0.8 V

Engineering Contradiction:

Improvetransistor sizeVSAvoidsub-threshold swing

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The patent changes the material parameter of the dielectric layer from conventional silicon-based materials to ferroelectric materials (such as HfZrO4, Pb(Zr,Ti)O3, or Pb1-xLaxZr1-yTiyO3). This material substitution fundamentally alters the electrical characteristics, enabling sub-threshold swing values less than 60 mV/dec and allowing operation voltages below 0.8 V while maintaining proper transistor scaling dimensions.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If the operation voltage is decreased to improve power efficiency, then power consumption decreases, but it becomes difficult to achieve operation voltage equal to or less than 0.8 V with conventional silicon-based transistors

Engineering Contradiction:

Improvepower consumptionVSAvoidoperation voltage

Core Design Contradiction:

Use of energy by moving objectVSEase of operation

Solution Approach 1:

By substituting the dielectric material with ferroelectric materials having high dielectric constants and specific phase structures, the patent achieves enhanced charge storage capability. This allows the transistor to operate at voltages of 0.8 V or lower while maintaining adequate on/off current ratios, thus reducing power consumption without sacrificing operational feasibility.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If conventional dielectric materials are used in the gate stack, then manufacturing is simpler, but the sub-threshold swing cannot be improved below 60 mV/dec

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidsub-threshold swing

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent employs composite material structures where ferroelectric materials (such as HfZrO4 or Pb-based perovskites) are integrated with existing transistor architectures. These composite structures combine the beneficial properties of ferroelectricity with compatible manufacturing processes, achieving sub-60 mV/dec sub-threshold swing while maintaining reasonable manufacturing complexity through established deposition and annealing techniques.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration decreases sub-threshold swing and improves electronic device performance by limiting current leakage and maintaining ferroelectricity effects, enabling better voltage amplification and scaling capabilities.

Implementation Method 1

a ferroelectric crystallization layer between the gate electrode and the substrate, the ferroelectric crystallization layer being at least partially crystallized and including a dielectric material having ferroelectricity or anti-ferroelectricity

Methodology Applied

Scientific EffectFerroelectricity:

Implementation Method 2

Methodology Applied

Scientific EffectAnti-ferroelectricity:

Implementation Method 3

a crystallization prevention layer between the ferroelectric crystallization layer and the substrate, the crystallization prevention layer including an amorphous dielectric material and being configured to prevent crystallization in the ferroelectric crystallization layer from spreading toward the substrate

Methodology Applied

Scientific EffectPhysical containment: Physical Containment

Implementation Method 4

forming a ferroelectric crystallization layer having ferroelectricity or anti-ferroelectricity by crystallizing at least a portion of the amorphous dielectric material layer through an annealing process

Methodology Applied

Scientific EffectCrystallization: Crystallisation

Implementation Method 5

Methodology Applied

Scientific EffectAnnealing: Annealing

Data Source

PatentUS11824118B2Electronic device and method of manufacturing the same

Publication Date: 2023.11.21 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.