Ferroelectric HfO2 Gate Stack for Lower Subthreshold Swing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing the subthreshold swing, which limits their performance and power efficiency, particularly in low power operation, due to the use of paraelectric high-k gate dielectric materials that do not exhibit negative-capacitance effects.
Innovation Solution
The integration of a ferroelectric layer with a stabilized crystalline phase, such as metastable orthorhombic phase of HfO2, into negative capacitance field effect transistors (NCFETs) using specific combinations of strain and composition, along with advanced manufacturing processes like atomic layer deposition, to create a negative-capacitance effect that improves subthreshold properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If paraelectric high-k gate dielectric materials are used, then the gate dielectric constant is improved, but the subthreshold swing cannot be reduced due to lack of negative-capacitance effects
Solution Approach 1:
The patent changes the material phase from paraelectric to ferroelectric, transforming the capacitance characteristics from positive to negative. This parameter change in the gate dielectric material enables the negative-capacitance effect, which directly addresses the subthreshold swing limitation while maintaining high-k properties
Solution Approach 2:
The patent employs composite material structures including ferroelectric HfO2-based materials combined with specific crystal phases (orthorhombic, tetragonal) and doping elements. This composite approach achieves both high dielectric constant and negative-capacitance effects, resolving the contradiction between dielectric performance and subthreshold characteristics
2Ease of manufacture
If conventional gate dielectric materials are used, then the manufacturing process is simple, but the device performance and power efficiency are limited
Solution Approach 1:
The patent utilizes atomic layer deposition (ALD) to precisely control the thickness and composition parameters of the ferroelectric layer, achieving optimal device performance through parameter optimization while maintaining compatibility with existing semiconductor manufacturing processes
Solution Approach 2:
The patent introduces localized ferroelectric regions with specific crystal phases and compositions within the gate dielectric structure. This local quality enhancement allows the device to achieve superior performance in critical areas while maintaining overall manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly lowers the subthreshold swing, enabling NCFETs to operate with a steep slope for low power consumption, thereby enhancing the operational efficiency and properties of semiconductor devices.
Implementation Method 1
The integration of a ferroelectric layer with a stabilized crystalline phase, such as metastable orthorhombic phase of HfO2, into negative capacitance field effect transistors (NCFETs) using specific combinations of strain and composition, along with advanced manufacturing processes like atomic layer deposition, to create a negative-capacitance effect that improves subthreshold properties
Implementation Method 2
advanced manufacturing processes like atomic layer deposition
Data Source
AI summary
In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.