Ferroelectric Gate Structure for Post-Fabrication Channel Strain Tuning

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Solution Overview

Problem

The strain introduced in transistor channels during fabrication can be lost, reducing carrier mobility and degrading device performance, and existing technologies lack the flexibility to adjust strain post-fabrication for optimal device performance.

Innovation Solution

Incorporating a ferroelectric layer, such as hafnium oxide-based materials, between the metal gate and spacer in semiconductor structures, allowing strain adjustment through applied bias voltage, enabling tensile or compressive strain in the channel region to optimize transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If strain is introduced in transistor channel during fabrication, then carrier mobility is improved, but strain is lost during fabrication operations reducing device performance

Engineering Contradiction:
Improvedevice performanceVSAvoidstrain in channel
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by introducing strain into the channel region before completing fabrication operations. The strain is intentionally created in advance (through source/drain extension formation or silicon germanium layer deposition) so that it is present during subsequent processing steps, rather than being applied after fabrication is complete. This preliminary strain introduction helps maintain device performance despite the challenging fabrication environment.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs parameter changes by varying the crystal orientation of the channel region (e.g., using <110> or <210> orientations instead of conventional <100>) and adjusting the composition of silicon germanium layers. These parameter changes enable the channel to accommodate and maintain strain throughout fabrication operations, as different crystal orientations and material compositions respond differently to mechanical stress and processing conditions.

Inventive Principle:
Principle #35Parameter changes

2Speed

If strain is introduced to improve carrier mobility, then transistor speed is enhanced, but flexibility to adjust strain post-fabrication is lost

Engineering Contradiction:
Improvetransistor operational speedVSAvoidstrain adjustment flexibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the strain state adjustable and reconfigurable after fabrication. Through the use of silicon germanium layers with controllable composition and thickness, or by applying external stress through dedicated structures, the strain in the channel can be dynamically tuned post-fabrication. This allows optimization of carrier mobility for different device requirements and enables adaptation to varying operational conditions without requiring complete fabrication rework.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for post-fabrication strain adjustment, enhancing carrier mobility and device performance by applying electrical fields, thereby improving the operational speed and flexibility of transistors.

Implementation Method 1

a ferroelectric layer between the metal gate layer and the substrate, wherein the ferroelectric layer is configured to cause a strain in the channel when applied with an electrical field

Methodology Applied
Scientific EffectFerroelectric effect:

Data Source

PatentUS11777031B2Semiconductor structure and manufacturing method for the semiconductor structure
Publication Date: 2023.10.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11777031B2 patent drawing
  • US11777031B2 patent drawing
  • US11777031B2 patent drawing

AI summary

The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.