Ferroelectric Gate Structure for Low-Voltage Subthreshold Swing Reduction
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Solution Overview
Problem
Existing silicon-based transistors face limitations in improving operating characteristics and scaling down due to high power density and subthreshold swing (SS) values, which restrict further device miniaturization and power reduction.
Innovation Solution
A semiconductor device incorporating a ferroelectric layer with a fixed charge region and a gate structure, where the ferroelectric layer has a dopant or oxygen vacancy concentration gradient, enabling a negative capacitance effect that lowers the subthreshold swing and allows for voltage amplification, thereby improving device performance and enabling smaller device scales.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing silicon-based transistors are used, then the device structure is simple and manufacturing is成熟, but the subthreshold swing is limited to about 60 mV/dec and power density increases with scaling
Solution Approach 1:
The patent introduces a fixed charge region with specific charge density (greater than 0 and less than 5 μC/cm²) in the ferroelectric layer to modify the electrical characteristics. This parameter change enables subthreshold swing below 60 mV/dec and reduces power density by allowing lower operating voltages
Solution Approach 2:
The patent employs a composite structure combining insulation layer, ferroelectric layer with fixed charge region, and gate. This composite material approach creates negative capacitance effect that improves subthreshold swing and reduces power consumption compared to conventional silicon-based transistors
2Productivity
If transistor size is reduced for scaling, then device density increases, but power density increases and operating voltage cannot be lowered below 0.8 V
Solution Approach 1:
By introducing fixed charge region with controlled charge density in the ferroelectric layer, the patent enables lower operating voltages and reduced power density, allowing continued device scaling without the 0.8 V voltage floor limitation of conventional transistors
Solution Approach 2:
The patent uses a thin fixed charge region (1 Å to 10 Å thickness) that can be formed through controlled dopant or oxygen vacancy concentration gradients, enabling scalable manufacturing while maintaining low power density characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a ferroelectric layer with a fixed charge region in the semiconductor device enhances the negative capacitance effect, reducing the subthreshold swing to below 60 mV/dec, enabling lower power consumption and smaller device scaling, thus overcoming the limitations of traditional silicon-based transistors.
Implementation Method 1
enabling a negative capacitance effect that lowers the subthreshold swing and allows for voltage amplification
Data Source
AI summary
Provided is a semiconductor device including a substrate on which a channel layer is provided, an insulation layer provided on the substrate, a ferroelectric layer provided on the insulation layer, a fixed charge region provided in the ferroelectric layer and containing charges of a predetermined polarity, and a gate provided on the ferroelectric layer. An absolute value of a charge density in the fixed charge region is greater than 0 and less than 5 μC/cm2.