Ferroelectric Semiconductor Device with Hafnium Oxide Layer
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Solution Overview
Problem
Current semiconductor technologies face challenges in developing negative capacitance field effect transistors (NCFETs) that effectively utilize ferroelectric materials to enhance operating characteristics, particularly in achieving stable ferroelectric properties and strain application for improved performance.
Innovation Solution
A ferroelectric semiconductor device is designed with a substrate, active region, gate insulating layer, ferroelectric layer made of hafnium oxide doped with specific metallic elements, and source/drain regions, where the ferroelectric layer is converted from an amorphous to a crystalline phase with a high proportion of orthorhombic crystals, applying compressive or tensile strain to improve transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ferroelectric layer is formed on a gate insulating layer to create an NCFET, then the transistor operating characteristics are enhanced through negative capacitance effect, but it is difficult to achieve stable ferroelectric properties and apply sufficient strain for optimal performance
Solution Approach 1:
The patent applies parameter changes by doping hafnium oxide with specific concentrations of aluminum (3-8 mol%), silicon (2-10 mol%), iridium (2-10 mol%), lanthanum (1-7 mol%), or gadolinium (1-7 mol%). These compositional parameter changes enable the formation of stable orthorhombic crystal phase (20% or more) and facilitate strain application, resolving the contradiction between achieving stable ferroelectric properties and ease of manufacture
Solution Approach 2:
The patent uses composite materials by creating a doped hafnium oxide system (HfO2 with Al, Si, Ir, La, or Gd) that combines the base ferroelectric material with dopant elements. This composite approach stabilizes the orthorhombic phase and enables controlled strain application, addressing both the reliability and manufacturability challenges
2Stability of the object's composition
If hafnium oxide is doped with metallic elements and annealed at high temperature to form crystalline phase, then ferroelectric stability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple functions into a single annealing process that simultaneously achieves dopant incorporation, crystal phase formation, and ferroelectric property stabilization. By combining these steps into one high-temperature annealing treatment (600-1000°C), the patent reduces overall process complexity while achieving the desired crystalline phase stability
Solution Approach 2:
The patent applies preliminary action by pre-doping the hafnium oxide layer with metallic elements before the annealing process. This preliminary dopant incorporation ensures that the subsequent annealing step can efficiently form the orthorhombic crystal phase without requiring additional complex processing steps, thereby reducing manufacturing complexity while achieving phase stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the operating characteristics of NCFETs by stabilizing ferroelectric properties and applying sufficient strain, resulting in improved performance and stability of the transistors.
Implementation Method 1
converting the amorphous ferroelectric layer into a crystalline ferroelectric layer
Implementation Method 2
annealing in a range from 800 to 1,000° C.
Implementation Method 3
applying compressive or tensile strain to improve transistor performance
Data Source
AI summary
A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.