Ferroelectric HfO2 Gate Stack for Thin-Film FET Scaling
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Solution Overview
Problem
Existing methods for forming high-k gate dielectric layers in semiconductor devices face challenges in achieving phase transformation of amorphous HfO2 to crystalline HfO2 at reduced thicknesses, leading to increased parasitic capacitance and reduced ferroelectricity, which affects device performance.
Innovation Solution
A method involving the application of an electric field during the deposition of a Hf-containing layer followed by an annealing process to promote the transformation of amorphous HfO2 to ferroelectric orthorhombic HfO2, using a sacrificial layer to facilitate selective deposition and control oxygen vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate dielectric layer thickness is reduced to scale down device geometry, then device density and integration are improved, but parasitic capacitance increases and ferroelectricity is reduced
Solution Approach 1:
The patent applies electric field during deposition and annealing processes to transform amorphous HfO2 into crystalline ferroelectric phase, changing the material's physical properties to achieve lower parasitic capacitance and improved ferroelectricity at reduced thicknesses
Solution Approach 2:
The patent utilizes phase transition of HfO2 from amorphous to crystalline ferroelectric phase through controlled annealing with electric field application, enabling the material to exhibit desirable ferroelectric properties at thin film thicknesses that reduce parasitic capacitance
2Length of moving object
If the gate dielectric layer thickness is reduced to scale down device geometry, then device density and integration are improved, but ferroelectricity is reduced
Solution Approach 1:
The patent modifies deposition and annealing parameters by applying electric field to induce crystalline ferroelectric phase formation in HfO2, maintaining strong ferroelectricity even at reduced thicknesses through controlled phase transformation
Solution Approach 2:
The patent employs controlled phase transition of HfO2 from amorphous to crystalline ferroelectric phase through annealing with electric field, ensuring robust ferroelectric properties are achieved and maintained at thin film thicknesses
3Ease of manufacture
If conventional deposition methods are used without electric field, then process simplicity is maintained, but phase transformation to crystalline HfO2 is insufficient
Solution Approach 1:
The patent applies electric field during the deposition and annealing processes as a preliminary action to promote complete phase transformation to crystalline HfO2, ensuring the material achieves desired ferroelectric properties before subsequent device fabrication steps
Solution Approach 2:
The patent modifies the deposition and annealing parameters by introducing electric field application, transforming the process to achieve complete crystalline phase formation while maintaining overall process feasibility and integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the ferroelectric properties of high-k gate dielectric layers, reducing subthreshold swing and parasitic capacitance, thereby improving the performance of field-effect transistors.
Implementation Method 1
promote the transformation of amorphous HfO2 to ferroelectric orthorhombic HfO2
Implementation Method 2
followed by an annealing process to promote the transformation
Implementation Method 3
using a sacrificial layer to facilitate selective deposition and control oxygen vacancies
Data Source
AI summary
A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.