In-Memory Computation with Ferroelectric Transistors for Signed Weight Neural Networks

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Solution Overview

Problem

Conventional computation apparatuses experience time delays and significant power consumption due to frequent data transfer between memory and computation units, particularly in neural networks, where unsigned weights complicate accuracy in complex networks.

Innovation Solution

A computation apparatus within a memory module that uses ferroelectric transistors and source follower amplifiers to perform multiplication operations with signed weights, reducing data transfer and power consumption by integrating computation and memory, and employing a pre-charge and discharge circuit to manage accumulation lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is frequently transferred between memory and computation apparatus, then computation can be performed, but time delay increases and power consumption increases

Engineering Contradiction:
Improvecomputation performanceVSAvoidtime delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent combines memory and computation apparatus into an integrated structure where computation units are embedded within the memory module. This merging eliminates the need for frequent data transfers between separate memory and computation components, thereby reducing time delay while maintaining computation performance.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If data is frequently transferred between memory and computation apparatus, then computation can be performed, but power consumption increases

Engineering Contradiction:
Improvecomputation performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The integrated memory-computation structure reduces power consumption by eliminating frequent data transfers between separate memory and computation components. The computation units perform operations directly on data stored in the memory array, significantly reducing the energy required for data movement.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If unsigned weight values are used in neural networks, then implementation is simpler, but accuracy cannot be ensured in complex networks

Engineering Contradiction:
Improveimplementation complexityVSAvoidcomputation accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent changes the parameter of weight representation from unsigned to signed values. The computation units are designed to handle signed weight values through differential voltage representations, enabling accurate computation in complex neural networks while maintaining manageable implementation complexity through the integrated architecture.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces time delays and power consumption while maintaining high accuracy in neural network computations, as demonstrated by improved inference accuracy with signed weights compared to unsigned weights.

Implementation Method 1

a source follower amplifier configured with a ferroelectric transistor to output a voltage corresponding to a result of the multiplication operation with respect to an input voltage provided to the word line

Methodology Applied
Scientific EffectFerroelectric effect:

Implementation Method 2

the ferroelectric transistor has a threshold voltage corresponding to the weight stored in the ferroelectric transistor

Methodology Applied
Scientific EffectThreshold voltage storage:

Data Source

PatentUS20240036827A1Computation apparatus in memory capable of computation of signed weight
Publication Date: 2024.02.01 UI (UNIVERSITY IND FOUNDATION) YONSEI UNIVERSITY
  • US20240036827A1 patent drawing
  • US20240036827A1 patent drawing
  • US20240036827A1 patent drawing

AI summary

There is provided a computation apparatus located in a memory module and configured to perform computation with data stored in the memory, the computation apparatus including: a plurality of word lines to which an input is provided; a plurality of unit arrays which store a weight having a sign and perform a multiplication operation on the input provided from the word line and the weight; and an accumulation line connected to the plurality of unit arrays and on which results of the multiplication operations performed by the plurality of unit arrays are accumulated, wherein each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation with respect to an input voltage provided to the word line.