Ferroelectric Interconnect Lining for Scaled FeRAM Read Margin
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Solution Overview
Problem
As feature sizes of integrated chips are scaled down, the area of the ferroelectric layer between the top and bottom electrodes in FeRAM devices decreases, making it difficult to accurately detect data states, and the process of forming FeRAM devices in trenches increases fabrication costs and design complexity.
Innovation Solution
The ferroelectric structure is integrated with conductive interconnect structures by extending along opposing sidewalls and bottom surfaces of conductive wire and via segments, allowing concurrent formation with the second conductive interconnect structure through a damascene process, thereby increasing the memory window and reducing fabrication costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes of integrated chips are scaled down, then device density and integration are improved, but the area of the ferroelectric layer between electrodes decreases making data detection difficult
Solution Approach 1:
The ferroelectric structure is configured to extend along the sidewalls of the conductive interconnect structure, transitioning from a planar area to a three-dimensional configuration. This dimensional change allows the ferroelectric layer to maintain sufficient area for accurate data detection even as feature sizes are scaled down, by utilizing the vertical sidewall space rather than only horizontal plane.
Solution Approach 2:
The ferroelectric structure is nested within or along the sidewalls of the conductive interconnect structure, effectively utilizing the existing interconnect geometry. This nesting approach allows the ferroelectric memory element to be integrated within the interconnect framework, maintaining functional area while accommodating scaled-down feature sizes.
2Measurement precision
If FeRAM devices are formed in trenches, then ferroelectric layer area can be maintained, but fabrication costs and design complexity increase
Solution Approach 1:
The ferroelectric structure formation is merged with the conductive interconnect structure formation process. By configuring the ferroelectric structure to extend along the sidewalls of the interconnect, both structures can be formed concurrently using the same damascene process, eliminating the need for separate trench formation and reducing fabrication complexity.
Solution Approach 2:
The damascene process used to form the conductive interconnect structure is made multi-functional by also forming the ferroelectric structure in the same process sequence. This universal approach allows a single fabrication process to accomplish multiple structural formations, reducing overall process complexity and cost.
3Measurement precision
If FeRAM devices are formed in trenches, then ferroelectric layer area can be maintained, but fabrication time and costs increase
Solution Approach 1:
The formation of the ferroelectric structure is combined with the formation of the second conductive interconnect structure in a single damascene process sequence. This merging of operations means that materials are deposited and patterned simultaneously for both structures, significantly reducing the total fabrication time compared to forming them as separate sequential steps.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip comprising a ferroelectric structure disposed between a first conductive interconnect structure and a second conductive interconnect structure. The first conductive interconnect structure overlies a substrate. The second conductive interconnect structure overlies the first conductive interconnect structure. The second conductive interconnect structure comprises a conductive wire segment directly overlying a conductive via segment. The ferroelectric structure continuously extends along opposing sidewalls and a bottom surface of the conductive wire segment and along opposing sidewalls and a bottom surface of the conductive via segment


