Ferroelectric Interconnect Lining for Denser FeRAM Sensing
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Solution Overview
Problem
As integrated chip feature sizes are scaled down, the area of the ferroelectric layer in FeRAM devices decreases, making it difficult to accurately detect data states, and the process of forming FeRAM devices in trenches increases fabrication costs and design complexity.
Innovation Solution
The ferroelectric structure is integrated with conductive interconnect structures, with layers extending along opposing sidewalls and bottom surfaces of conductive wire and via segments, increasing the area of the ferroelectric layer and forming the ferroelectric structure concurrently with the second conductive interconnect structure using a damascene process to reduce processing steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FeRAM devices are formed in trenches, then data storage capability is maintained, but fabrication cost and design complexity increase
Solution Approach 1:
The patent merges the FeRAM device formation with the conductive interconnect structure by integrating the ferroelectric layer, electrode layers, and memory cavity directly into the interconnect formation process. This eliminates separate trench formation steps and reduces design complexity while maintaining data storage capability.
Solution Approach 2:
The conductive interconnect structure serves multiple functions: it provides electrical interconnection and simultaneously houses the FeRAM memory cell. The memory cavity within the interconnect structure serves as both the storage element and the defining feature for subsequent processing steps, reducing overall device complexity.
2Productivity
If feature sizes are scaled down, then device density increases, but ferroelectric layer area decreases making data state detection difficult
Solution Approach 1:
The patent transitions from a planar ferroelectric layer geometry to a three-dimensional structure where the ferroelectric layer lines the walls and bottom of a memory cavity. This vertical dimension allows the ferroelectric layer to maintain sufficient area for accurate data state detection even when lateral feature sizes are scaled down, thereby increasing device density without sacrificing measurement precision.
Solution Approach 2:
The ferroelectric layer is nested within the memory cavity formed by the conductive interconnect structure. This nested configuration allows the ferroelectric layer to utilize the vertical walls of the cavity, effectively increasing its surface area relative to the lateral footprint, thus maintaining detection accuracy while achieving higher device density.
3Ease of manufacture
If ferroelectric structure is integrated with conductive interconnect structure, then processing steps and costs decrease, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming the memory cavity and depositing the ferroelectric layer and electrode layers during the interconnect formation process itself, before final patterning steps. This preliminary integration reduces the number of subsequent processing steps and associated costs, while the established cavity geometry provides precise alignment references for subsequent manufacturing steps.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip comprising a ferroelectric structure disposed between a first conductive interconnect structure and a second conductive interconnect structure. The first conductive interconnect structure overlies a substrate. The second conductive interconnect structure overlies the first conductive interconnect structure. The second conductive interconnect structure comprises a conductive wire segment directly overlying a conductive via segment. The ferroelectric structure continuously extends along opposing sidewalls and a bottom surface of the conductive wire segment and along opposing sidewalls and a bottom surface of the conductive via segment