Ferroelectric Latch Circuit for Power Disruption Continuity
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Solution Overview
Problem
Existing logic circuits that need to operate during power disruptions face challenges in maintaining system state due to limitations in energy storage and complexity in using non-volatile memory for state storage, particularly with ferroelectric memory devices requiring separate save/restore procedures and being prone to data alteration during power instability.
Innovation Solution
A ferroelectric latch comprising autonomous memory cells with current controllers and ferroelectric capacitors, which allows for continuous operation across power disruptions by utilizing current mirrors and current limiters to manage voltage and current flow, ensuring data integrity and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory devices are used to store system state, then data retention during power disruption is improved, but device complexity and operational complexity increase due to separate save/restore procedures
Solution Approach 1:
The patent combines the volatile latch functionality with non-volatile ferroelectric memory functionality into a single integrated circuit structure. The ferroelectric latch circuit integrates the state storage and power-loss recovery functions, eliminating the need for separate save/restore procedures and external non-volatile memory devices. This merging reduces overall system complexity while maintaining data retention capability.
Solution Approach 2:
The ferroelectric latch circuit performs multiple functions simultaneously: it operates as a conventional volatile latch during normal operation and automatically recovers state after power loss without requiring separate save/restore modes. The circuit adapts its behavior based on power availability, providing both volatile-speed operation and non-volatile data retention in a single universal component.
2Adaptability or versatility
If ferroelectric memory devices operate at normal logic levels, then compatibility with logic circuitry is improved, but data integrity deteriorates during power instability due to potential data alteration
Solution Approach 1:
The circuit employs preliminary protective actions during power transitions. Detection circuits monitor power stability and activate protection mechanisms before data corruption can occur. During power-up and power-down transitions, the circuit prevents spurious voltage changes from altering the ferroelectric capacitor state by enabling protective circuitry that blocks unwanted write operations during unstable periods.
Solution Approach 2:
The patent introduces intermediary detection circuits and control logic that mediate between the power supply and the ferroelectric latch. These intermediary circuits monitor power stability and control when write operations to the ferroelectric capacitor are permitted, preventing direct exposure of the memory element to harmful power fluctuations while maintaining normal logic level operation.
3Ease of operation
If conventional latches are used for continuous operation, then operational simplicity is maintained, but operation during power disruption cannot be sustained
Solution Approach 1:
The patent changes the fundamental parameter of voltage retention in the latch circuit by incorporating ferroelectric capacitors that can maintain their polarized state without continuous power supply. During normal operation, the circuit behaves like a conventional volatile latch with standard refresh characteristics. During power loss, the ferroelectric capacitors retain their voltage state, enabling the latch to maintain its output state indefinitely without power, thus extending operational duration while preserving operational simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ferroelectric latch provides seamless continuity of system state across power disruptions, reduces complexity, and prevents data alteration during power instability, enhancing reliability and efficiency in logic circuit operations.
Implementation Method 1
A ferroelectric latch that includes first and second autonomous memory cells is disclosed. The first autonomous memory cell characterized by a first current controller having by a first current controller input that controls a first current that flows between a first node and a power rail. In addition, the first autonomous memory cell includes a first ferroelectric capacitor connected to the first node and the first current controller input
Data Source
AI summary
A ferroelectric latch that includes first and second autonomous memory cells. The first autonomous memory cell has a first current controller that controls a first current that flows between a first node and a power rail. The first autonomous memory cell includes a first ferroelectric capacitor connected to the first node and the first current controller input; and a first conductive load connected to the first node and a second power rail. The second autonomous memory cell includes a second current controller that controls a second current that flows between a second node and the power rail; a second ferroelectric capacitor connected to the second node and the second current controller input, and a second conductive load connected to the second node and the second power rail. The first node is connected to the second current controller input, and the second node is connected between the first current controller input and the second node.