Ferroelectric Memory Latch for Logic State Retention Through Power Loss
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Solution Overview
Problem
Existing logic circuits that operate across power disruptions face limitations due to the need for separate save/restore modes and complexity in using non-volatile memory, especially when voltages and cycle times differ from the logic circuitry, and ferroelectric memory devices require synchronous operations, making it challenging to maintain system state during power instability.
Innovation Solution
A circuit with an autonomous memory latch (AML) that includes a ferroelectric capacitor, a conductive load, and a switch with a current-actuated control input, allowing the AML to maintain its state across power disruptions by using a feedback loop and switch control to prevent state changes during power transitions, enabling direct tracking and preservation of system state without additional save/restore procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory is used to store system state, then system state can be preserved across power disruptions, but the system requires separate save/restore modes and operates at different logic levels than the logic circuitry
Solution Approach 1:
The patent merges the non-volatile memory functionality directly into the logic circuit by using a ferroelectric capacitor as part of the latch structure itself. This integration eliminates the need for separate save/restore modes and allows the memory to operate at the same logic levels as the logic circuitry, resolving the contradiction between reliability and device complexity
Solution Approach 2:
The ferroelectric latch serves multiple functions simultaneously: it acts as both a logic element and a non-volatile memory device. This multi-functionality allows the same circuit to perform logic operations and preserve state across power disruptions without requiring separate dedicated memory components or save/restore procedures
2Speed
If ferroelectric memory devices are used, then real-time tracking of system state is possible, but synchronous read/write operations are required which complicates power disruption handling
Solution Approach 1:
The ferroelectric latch automatically maintains its state without requiring external control signals or synchronous operations. The intrinsic hysteresis of the ferroelectric material allows the device to self-preserve its state through the entire power cycle, eliminating the need for complex synchronous read/write control mechanisms
3Reliability
If ferroelectric memory is used to store system state, then state can be preserved, but preventing data alteration during power instability becomes challenging
Solution Approach 1:
The patent positions switches to open the ferroelectric latch from the logic circuit before power disruptions occur. This preemptive isolation protects the stored data from alteration during power instability, while the ferroelectric capacitor's inherent non-volatility ensures the state is already preserved and ready for recovery
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The AML circuit effectively preserves the system state across power disruptions, reducing complexity and cost by allowing real-time tracking and maintaining system integrity during power fluctuations, as it operates at the same logic levels as the circuitry and does not require separate save/restore modes.
Implementation Method 1
The autonomous memory circuit includes a ferroelectric capacitor
Data Source
AI summary
A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.