Ferroelectric Latch Stability Margin Test via Differential Plate Bias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric capacitors in non-volatile memory and logic circuits are vulnerable to degradation due to repeated read/write cycles and environmental factors, leading to data errors and early device failure, necessitating an effective screening method to identify and remove weak capacitors before they fail.
Innovation Solution
A method and circuit for accurately screening non-volatile circuits with ferroelectric capacitors by performing a stability margin test using reduced voltage on separate plate lines during the restore operation, followed by accelerated stress testing, to determine the reliability margin and remove potential failure risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional screening methods are used for ferroelectric capacitors, then manufacturing process is simple, but measurement precision is insufficient to accurately identify weak capacitors
Solution Approach 1:
The patent divides the screening process into multiple stages: initial capacitance measurement, stability margin test with reduced voltage, and accelerated stress testing. This segmented approach allows progressive identification of weak capacitors, improving measurement precision while managing test circuit complexity through modular testing procedures.
Solution Approach 2:
The patent performs preliminary characterization of ferroelectric capacitors during manufacturing by measuring capacitance values and conducting stability margin tests before devices are deployed. This preliminary action identifies weak capacitors early, enabling their removal from the product population before they can cause failures in actual application.
2Reliability
If reduced voltage stability margin test is performed, then reliability assessment is improved, but use of energy increases during testing
Solution Approach 1:
The patent applies reduced voltage (partial action) during the stability margin test instead of full operating voltage, which is sufficient to identify weak capacitors while consuming less energy. The reduced voltage level is carefully selected to maintain test effectiveness while reducing energy consumption during the screening process.
Solution Approach 2:
The testing procedure uses periodic voltage application with specific pulse widths and intervals, allowing capacitors to be tested in discrete cycles. This periodic action enables reliable identification of weak devices while managing energy consumption through controlled test duration and voltage pulse timing.
3Reliability
If accelerated stress testing is conducted, then reliability screening is improved, but duration of action of stationary object increases
Solution Approach 1:
The patent changes temperature and voltage parameters during accelerated stress testing to simulate long-term degradation in a compressed time frame. By elevating temperature and applying stress voltages, the test accelerates aging effects that would normally occur over months or years, enabling reliable screening within hours while maintaining screening effectiveness.
Solution Approach 2:
The testing methodology exploits phase transitions in ferroelectric material polarization states during stress testing. By monitoring transitions between polarized and depolarized states under accelerated conditions, the test efficiently identifies capacitors with degraded reliability without requiring extended testing durations.
Data Source
AI summary
Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.