2D Seeded Ferroelectric Layer Alignment for Low-Voltage Transistors
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Solution Overview
Problem
Existing silicon-based electronic devices face limitations in reducing operating voltage and scaling down due to subthreshold swing limitations, leading to increased power density.
Innovation Solution
The development of electronic devices with a ferroelectric layer aligned within ±30 degrees relative to a (111) crystal direction, utilizing a seed layer with a 2D material, to enhance subthreshold swing characteristics and decrease operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If silicon-based logic transistor size is decreased, then scaling down is achieved, but operating voltage cannot be decreased to 0.8V or less due to subthreshold swing limitation
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductors to black phosphorus semiconductor, which has different electrical characteristics including lower subthreshold swing values (below 60 mV/dec), enabling operating voltages of 0.8V or less while maintaining scaled-down transistor dimensions
Solution Approach 2:
The patent employs a composite structure combining black phosphorus semiconductor channel layer with specific gate dielectric materials and electrode structures, creating a multi-material system that achieves both small size and low operating voltage through synergistic material properties
2Volume of moving object
If silicon-based logic transistor size is decreased, then scaling down is achieved, but power density increases
Solution Approach 1:
By transitioning to black phosphorus semiconductor with superior subthreshold swing characteristics (below 60 mV/dec), the patent reduces leakage current and power consumption at scaled dimensions, thereby decreasing power density while maintaining small transistor size
Solution Approach 2:
The patent converts the potential harm of increased power density from miniaturization into a benefit by using black phosphorus materials that inherently provide lower power consumption at small scales, turning the scaling challenge into an opportunity for improved power efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases the operating voltage and improves the operational performance and efficiency of electronic devices by increasing capacitance and reducing power consumption.
Implementation Method 1
The ferroelectric layer may have ferroelectric or anti-ferroelectric properties
Implementation Method 2
The ferroelectric layer may have ferroelectric or anti-ferroelectric properties
Implementation Method 3
The seed layer may have a lattice constant having a magnitude that is in a range of about 90% to about 110% with respect to a magnitude of a lattice constant of the ferroelectric layer
Data Source
AI summary
An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.