Planar Ferroelectric Majority Gates for Compact Low-Power Logic

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Solution Overview

Problem

Conventional CMOS transistors require a large number of MOSFETs to implement majority gates, leading to increased area and power consumption, and slower operation in logic circuits.

Innovation Solution

The development of three-input planar ferroelectric majority gates with a capacitor structure, utilizing a planar ferroelectric layer and asymmetric or symmetric input electrodes, which reduce the number of devices needed, resulting in a more compact and efficient solution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional CMOS transistors are used to implement majority gates, then the gates can be integrated into existing CMOS processes, but the number of MOSFETs required increases area and power consumption

Engineering Contradiction:
Improvecompatibility with CMOS processVSAvoidarea consumed by majority gate
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges multiple MOSFET functions into a single majority gate unit by sharing common transistors among multiple gate implementations. The common transistors are shared between majority gate and logic circuit functions, reducing the total device count from 12-18 MOSFETs to fewer devices while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention creates multi-functional circuit elements where the same physical transistors serve multiple logical purposes. The majority gate transistors simultaneously function as logic gate components and as part of the broader logic circuit architecture, allowing one set of devices to perform what previously required separate dedicated components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of manufacture

If conventional CMOS transistors are used to implement majority gates, then the gates can be integrated into existing CMOS processes, but power consumption increases

Engineering Contradiction:
Improvecompatibility with CMOS processVSAvoidpower consumption of majority gate
Core Design Contradiction:
Ease of manufactureVSUse of energy by stationary object

Solution Approach 1:

The patent merges multiple MOSFET functions into a single majority gate unit by sharing common transistors among multiple gate implementations. The common transistors are shared between majority gate and logic circuit functions, reducing the total device count from 12-18 MOSFETs to fewer devices while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention creates multi-functional circuit elements where the same physical transistors serve multiple logical purposes. The majority gate transistors simultaneously function as logic gate components and as part of the broader logic circuit architecture, allowing one set of devices to perform what previously required separate dedicated components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If conventional CMOS transistors are used to implement majority gates, then the gates can be integrated into existing CMOS processes, but operation speed decreases

Engineering Contradiction:
Improvecompatibility with CMOS processVSAvoidoperation speed of majority gate
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent merges multiple MOSFET functions into a single majority gate unit by sharing common transistors among multiple gate implementations. The common transistors are shared between majority gate and logic circuit functions, reducing the total device count from 12-18 MOSFETs to fewer devices while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention creates multi-functional circuit elements where the same physical transistors serve multiple logical purposes. The majority gate transistors simultaneously function as logic gate components and as part of the broader logic circuit architecture, allowing one set of devices to perform what previously required separate dedicated components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If more MOSFETs are used to implement majority gates, then the gates can be fully integrated into CMOS logic circuits, but device complexity increases

Engineering Contradiction:
Improveintegration capability into logic circuitsVSAvoidnumber of MOSFETs in majority gate
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple MOSFET functions into a single majority gate unit by sharing common transistors among multiple gate implementations. The common transistors are shared between majority gate and logic circuit functions, reducing the total device count from 12-18 MOSFETs to fewer devices while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention creates multi-functional circuit elements where the same physical transistors serve multiple logical purposes. The majority gate transistors simultaneously function as logic gate components and as part of the broader logic circuit architecture, allowing one set of devices to perform what previously required separate dedicated components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The ferroelectric majority gates consume less area and power while operating faster than CMOS implementations, enabling more efficient logic circuit operation.

Implementation Method 1

the ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer at the output electrode becomes polarized in the direction of polarization of the majority of the inputs

Methodology Applied
Scientific EffectFerroelectric polarization: Polarisation

Data Source

PatentUS20250311310A1Planar ferroelectric majority gates
Publication Date: 2025.10.02 INTEL CORP
  • US20250311310A1 patent drawing
  • US20250311310A1 patent drawing
  • US20250311310A1 patent drawing

AI summary

Technologies for planar three-input ferroelectric majority gates are disclosed. In one embodiment, a ferroelectric layer has asymmetric input electrodes and an output electrode located on a surface of the ferroelectric layer. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer at the output electrode becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs. Symmetric input electrodes are utilized in other ferroelectric majority gate embodiments.