Ferroelectric Memory Array With Auxiliary Gate Segmentation
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Solution Overview
Problem
Ferroelectric memory devices require further improvements in aspects such as threshold voltage control and memory window management to enhance data storage capabilities and prevent accidental data overwrite.
Innovation Solution
Incorporating an auxiliary gate capacitively coupled to the channel layer, which allows for the switching between first and second polarization states of the ferroelectric layer, enabling a sufficient memory window without increasing the voltage difference between the gate and source/drain electrodes, and allowing for compact array arrangement with shared source/drain electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ferroelectric memory device structure is used, then the device can store data using polarization states, but the memory window is insufficient and threshold voltage control is poor
Solution Approach 1:
The gate control is segmented into two independent gates: a main gate and an auxiliary gate. This segmentation allows independent control of threshold voltage and memory window, resolving the contradiction by enabling sufficient memory window with controlled threshold voltage without requiring a completely new device structure.
Solution Approach 2:
An auxiliary gate is introduced as an intermediary element between the control circuit and the ferroelectric layer. This auxiliary gate mediates the control of threshold voltage independently from the main gate, allowing precise threshold voltage control while maintaining sufficient memory window through the main gate's voltage application.
2Reliability
If voltage is increased to ensure sufficient memory window, then data storage capability improves, but accidental data overwrite risk increases
Solution Approach 1:
The voltage control is segmented into two independent components: the main gate controls the memory window for data storage capability, while the auxiliary gate independently controls the threshold voltage to prevent accidental overwrite. This segmentation eliminates the need to increase overall voltage, as each gate operates independently to achieve its specific function.
Solution Approach 2:
The threshold voltage is controlled by changing the voltage parameter on the auxiliary gate independently, rather than increasing the main gate voltage. This parameter change on the auxiliary gate adjusts the threshold voltage to prevent accidental overwrite while the main gate maintains sufficient memory window for reliable data storage.
3Ease of operation
If separate source/drain electrodes are used for each memory device, then device operation is simplified, but memory array density decreases
Solution Approach 1:
Adjacent memory devices share common source and drain electrodes, merging the electrode structures. This merging reduces the total number of electrodes required, increasing memory array density. The selective operation of each device is maintained through independent gate control, preserving ease of operation despite the shared electrode structure.
Solution Approach 2:
The shared source and drain electrodes serve multiple memory devices simultaneously, giving these electrodes universal functionality. Each electrode structure performs the function of source/drain for multiple devices, increasing density while the multi-functionality is managed through independent gate control that selectively activates specific devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures a sufficient memory window, prevents accidental overwrite, and allows for a more compact and high-density memory array design, enabling efficient binary data storage and read operations.
Implementation Method 1
an auxiliary gate capacitively coupled to a channel layer from a back side of the channel layer
Implementation Method 2
Information can be stored as a certain polarization state in the ferroelectric material, and such polarization state can be maintained even in absence of a voltage applied across the ferroelectric material
Data Source
AI summary
A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.