Ferroelectric Memory Channel with Back Gate for Read Disturb Relief
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Solution Overview
Problem
High voltage application during read operations in semiconductor memory devices can degrade reliability and cause performance issues due to the read disturb phenomenon.
Innovation Solution
Incorporating a back gate electrode in the channel structure with a ferroelectric layer, channel layer, and mold structure, and applying a back gate voltage during read operations to alleviate the read disturb phenomenon by reducing the voltage applied to unselect word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If high voltage is applied to the target cell and other cells for channel formation during read operation, then the read operation can be performed, but the reliability of the memory cell degrades due to read disturb phenomenon
Solution Approach 1:
The gate structure is segmented into two independent gates: a front gate (word line) for selecting the target cell and a back gate for controlling the channel formation. This segmentation allows independent voltage control, enabling the back gate voltage to be adjusted to prevent read disturb in non-selected cells while maintaining proper read operation in the selected cell.
Solution Approach 2:
The patent introduces a new voltage parameter (back gate voltage) that can be independently controlled from the word line voltage. By changing the back gate voltage parameter, the channel formation condition can be precisely controlled to enable read operation while preventing read disturb phenomenon in non-selected cells, thus improving reliability.
2Quantity of substance
If three-dimensional arrangement of memory cells is used to increase data storage capacity, then the storage capacity increases, but the channel length increases which may cause performance degradation
Solution Approach 1:
The patent transitions from a planar gate configuration to a three-dimensional stacked gate configuration with front and back gates positioned at different vertical levels. This dimensional change allows the channel to be effectively controlled by multiple gates along its length, compensating for the increased channel length associated with higher storage capacity in 3D architectures.
Solution Approach 2:
By introducing the back gate voltage parameter, the patent provides an additional degree of freedom for controlling channel formation. This parameter control mechanism compensates for the performance degradation caused by increased channel length, allowing maintainment of proper transistor operation even as channel length increases with higher storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the reliability of semiconductor memory devices by reinforcing read current and preventing performance degradation, even with increased channel length and capacity.
Implementation Method 1
a channel structure extending through the mold structure and including a ferroelectric layer, a channel layer, and a back gate electrode stacked in turn on a side surface of the plurality of gate electrodes
Data Source
AI summary
An example semiconductor memory device includes a cell substrate, a mold structure, and a channel structure. The cell substrate includes a first side and a second side opposite to the first side. The mold structure includes a plurality of gate electrodes and a plurality of mold insulating films alternately stacked on the first side of the cell substrate. The channel structure extends through the mold structure and includes a ferroelectric layer, a channel layer, and a back gate electrode stacked in turn on a side surface of the plurality of gate electrodes. The plurality of gate electrodes and the channel structure may define a plurality of memory cells, and during a read operation of a select memory cell of the plurality of memory cells, a back gate voltage May be applied to the back gate electrode of the channel structure.