Ferroelectric Memory Using Buried Recessed Access Devices
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Solution Overview
Problem
Current ferroelectric random access memory (FeRAM) cells have limitations in terms of cell density and footprint due to the use of planar transistors and parallel plate capacitors, which hinder their ability to achieve high memory density and fast operation while maintaining non-volatile properties.
Innovation Solution
The implementation of a ferroelectric memory array with buried recessed access devices (BRADs) and container-style ferroelectric capacitors, which are formed on pitch with BRADs, allowing for a smaller feature size and increased cell density, achieving a 4F2 cell size by using atomic layer deposition for ferroelectric material formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar transistors and parallel plate capacitors are used in FeRAM cells, then the device structure is simple and easy to manufacture, but the cell density and footprint are limited
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional buried recessed access device structures. The BRAD extends vertically into the substrate with a depth greater than its width, creating a vertical channel that increases storage capacity without increasing footprint area. This dimensional transition enables higher cell density while managing structural complexity through vertical integration rather than lateral expansion.
Solution Approach 2:
The container-style ferroelectric capacitor is formed within a recessed region in the substrate, nesting the capacitor structure within the existing substrate volume. The BRAD is positioned within a recessed access device region that is itself formed in the substrate, creating nested vertical structures. This nesting approach maximizes space utilization and increases cell density without proportionally increasing device complexity.
2Manufacturing precision
If larger feature sizes are used to simplify manufacturing, then manufacturing precision requirements are reduced, but memory density and operational speed decrease
Solution Approach 1:
The patent employs atomic layer deposition (ALD) to precisely control the thickness and composition of ferroelectric material layers at the nanometer scale. ALD enables accurate deposition of thin films with controlled stoichiometry, allowing the formation of complex multi-layer ferroelectric capacitor structures with precise parameter control. This advanced deposition technique maintains manufacturing precision while enabling smaller feature sizes and higher density.
Solution Approach 2:
The patent replaces traditional photolithography-based patterning with self-aligned formation methods for the BRAD and capacitor structures. The recessed regions and vertical structures are formed through sequential deposition and etching processes that automatically align features without requiring high-precision photomask alignment. This substitution reduces the manufacturing precision burden on lithography while enabling smaller features through better process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances cell density and reduces the footprint of FeRAM cells, enabling faster programming and reading while maintaining non-volatile data retention, surpassing previous approaches in terms of memory density and operational speed.
Implementation Method 1
achieving a 4F2 cell size by using atomic layer deposition for ferroelectric material formation
Data Source
AI summary
Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.