Ferroelectric Memory Carrier Structures for Wider Memory Window
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Solution Overview
Problem
Ferroelectric memory devices face challenges with limited memory window and high leakage current due to insufficient minority carrier polarization, which affects their performance and efficiency.
Innovation Solution
Incorporation of carrier structures made of specific materials (e.g., NiO, Cu2O, CuAlO2) connected to source/bit lines, providing extra minority carriers to enhance polarization of memory segments and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric memory structure is used, then device simplicity is maintained, but memory window is limited and leakage current is high
Solution Approach 1:
The patent divides the memory device into distinct functional regions by introducing carrier structures that are spatially separated from the main memory array. These carrier structures are positioned in isolation trenches and separated by dielectric materials, creating segmented functional zones that independently manage carrier generation and storage, thereby improving memory window without excessive complexity increase
Solution Approach 2:
The patent introduces dielectric materials as intermediary elements between the carrier structures and the memory array. These dielectric layers act as mediators that electrically isolate the carrier structures from direct contact with the memory cells, allowing carrier injection while preventing unwanted interference, thus improving performance with controlled complexity
2Reliability
If conventional memory structure without carrier structures is used, then device complexity is low, but leakage current is high
Solution Approach 1:
The patent extracts the carrier generation function from the main memory array by creating separate carrier structures in isolation trenches. This extraction allows the carrier structures to be optimized specifically for carrier generation and storage, reducing leakage current in the memory array while maintaining overall device functionality with added but manageable complexity
Solution Approach 2:
The patent applies local quality by creating specific regions with different functional properties. The carrier structures are positioned in specific locations (isolation trenches) and made from specific materials (e.g., NiO, Cu2O, CuAlO2) to provide localized carrier generation and storage capabilities, reducing leakage current at critical points without requiring global structural changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of carrier structures increases the memory window by at least 30% and decreases leakage current by at least 60%, improving the overall performance of ferroelectric memory devices.
Implementation Method 1
Ferroelectric memory devices face challenges with limited memory window and high leakage current due to insufficient minority carrier polarization
Implementation Method 2
Ferroelectric memory devices face challenges with limited memory window and high leakage current due to insufficient minority carrier polarization
Data Source
AI summary
A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.