Ferroelectric Memory Array Carrier Structures for Leakage Reduction
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Solution Overview
Problem
Ferroelectric memory devices face challenges in achieving an optimal memory window and minimizing leakage current due to insufficient minority carrier polarization in the erase state.
Innovation Solution
Incorporation of carrier structures made of specific materials (e.g., NiO, Cu2O, CuAlO2) connected to source/bit lines, which provide additional minority carriers to enhance polarization of memory segments, thereby increasing the memory window and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric memory device structure is used, then device simplicity is maintained, but memory window is insufficient and leakage current is high
Solution Approach 1:
The device is segmented into distinct functional regions: memory segments containing ferroelectric memory cells, carrier structures providing minority carriers, and isolation structures separating adjacent components. This segmentation allows each component to perform its specific function optimally, resolving the contradiction by improving memory window through specialized structures without requiring complete redesign of the entire device.
Solution Approach 2:
Isolation structures serve as intermediaries between memory segments and carrier structures, preventing direct unwanted interactions while allowing each component to function independently. The isolation structures mediate the relationship between different device components, enabling improved memory window and reduced leakage current without compromising device simplicity through excessive interconnections.
2Reliability
If carrier structures are added to provide minority carriers, then memory window increases and leakage current decreases, but device complexity increases
Solution Approach 1:
Carrier structures are strategically placed in specific locations where minority carriers are needed, rather than uniformly distributed throughout the device. This local quality approach allows the carrier structures to be positioned precisely where they can most effectively reduce leakage current and improve memory window, minimizing unnecessary complexity in regions where carrier injection is not required.
Solution Approach 2:
The device employs composite material structures combining ferroelectric materials in memory segments with carrier-injecting materials in carrier structures. This composite approach allows each material to contribute its specific properties: the ferroelectric material provides non-volatile memory functionality while the carrier structure materials provide minority carriers, achieving improved reliability without requiring a complete material system redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of carrier structures results in a 30% improvement in memory window and a 60% decrease in leakage current compared to devices without these structures.
Implementation Method 1
Incorporation of carrier structures made of materials like NiO, Cu2O, or IGZO, which provide additional minority carriers to enhance polarization of memory segments
Data Source
AI summary
A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.