Ferroelectric Memory Cell Amorphous Layer Leakage Current
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Solution Overview
Problem
Ferroelectric memory devices face issues with charge trapping, leading to increased leakage current, reduced lifetime, and inaccurate sensing due to the thin nature of HfO2 layers, which complicates the maintenance of the polarization state and memory window.
Innovation Solution
Incorporating an amorphous layer between ferroelectric oxide storage layers, along with suitable dopants, to reduce crystal formation and enhance the endurance of the ferroelectric structure, and employing a write voltage pulse sequence that includes a detrapping pulse to minimize charge trapping and improve sensing times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If HfO2 layer thickness is reduced to maintain ferroelectric properties, then device integration and scaling are improved, but charge trapping becomes more critical and leakage current increases
Solution Approach 1:
The patent employs a composite ferroelectric structure consisting of multiple HfO2 layers with different compositions and crystalline phases. The first HfO2 layer has a first composition and crystalline phase, while the second HfO2 layer has a second composition and crystalline phase. This composite approach allows each layer to contribute different properties, reducing charge trapping while maintaining ferroelectric functionality at reduced thickness.
Solution Approach 2:
The patent applies local quality by creating distinct regions within the ferroelectric structure with different compositions and phases. The first HfO2 layer is positioned adjacent to the gate electrode interface, while the second HfO2 layer is positioned away from the interface. Each layer is locally optimized with specific compositions to address charge trapping at different locations within the structure.
2Volume of moving object
If HfO2 layer thickness is reduced, then device scaling is improved, but leakage current increases
Solution Approach 1:
The composite structure of two HfO2 layers with different compositions and phases creates a more robust barrier against leakage current. The first HfO2 layer with its specific composition and phase adjacent to the gate interface provides one level of protection, while the second HfO2 layer provides additional protection, collectively reducing leakage current despite reduced overall thickness.
Solution Approach 2:
By optimizing the composition and phase of HfO2 layers at different locations within the structure, the patent locally addresses leakage current pathways. The first HfO2 layer is locally optimized for interface stability, while the second HfO2 layer is optimized for bulk properties, collectively reducing leakage current throughout the structure.
3Reliability
If dopant species are incorporated into HfO2 layer, then remanent polarization is improved, but device complexity increases
Solution Approach 1:
The patent changes compositional parameters by incorporating dopant species into the HfO2 layers at controlled concentrations. The first HfO2 layer has a first dopant concentration and the second HfO2 layer has a second dopant concentration, allowing optimization of remanent polarization through parameter adjustment rather than structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current, charge trapping, and enhances the reliability and endurance of ferroelectric memory cells, allowing for faster and accurate sensing operations without disturbing the ferroelectric state.
Implementation Method 1
The switching is caused by applying an electrical field via voltage between transistor gate and transistor channel. Specially, for n-channel transistors, ferroelectric switching after application of a sufficiently high positive voltage pulse causes a shift of the threshold voltage to lower or negative threshold voltage values.
Implementation Method 2
The intermediate amorphous layer prevents the formation of crystals within the ferroelectric structure that extend throughout the entire dimension of the thickness of the ferroelectric structure.
Data Source
AI summary
An integrated circuit includes a ferroelectric memory cell. In one embodiment, the ferroelectric memory cell includes a first oxide storage layer, a second oxide storage layer, and an amorphous layer disposed between the first and second oxide storage layers. Each of the first and second oxide storage layers includes a ferroelectric material that is at least partially in a ferroelectric state and further includes, as main components, oxygen and any of the group consisting of Hf, Zr and (Hf,Zr).