Ferroelectric Memory Cell Without Plate Line
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Solution Overview
Problem
Ferroelectric memory circuits using lead zirconate Titanate (PZT) face challenges with high programming voltage reducing endurance and providing slow read and write speeds, while low programming voltage for volatile operations increases endurance but requires frequent data refresh, and the need for a separate plate line increases the size of memory cells.
Innovation Solution
A ferroelectric static random access memory (FeSRAM) cell design that eliminates the plate line by using four ferroelectric capacitors coupled across power supply and ground reference voltage signals, allowing for programming without a plate line and achieving compact size comparable to conventional SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If high programming voltage is applied to achieve non-volatile storage, then data retention is improved, but endurance deteriorates and read/write speed decreases
Solution Approach 1:
The patent implements dynamic voltage switching capability in the ferroelectric capacitor, allowing it to operate in two modes: high voltage mode for non-volatile storage and low voltage mode for volatile operations. This dynamic adaptability enables the system to switch between retention-optimized and endurance-optimized states, resolving the contradiction between data retention time and reliability.
Solution Approach 2:
The patent changes the operating voltage parameter of the ferroelectric capacitor based on operational requirements. By adjusting the voltage level applied to the capacitor, the system can achieve either non-volatile storage (with longer retention but reduced endurance) or volatile storage (with higher endurance and faster speeds), thus resolving the contradiction through parameter adaptation.
2Duration of action of stationary object
If high programming voltage is applied to achieve non-volatile storage, then data retention is improved, but read/write speed decreases
Solution Approach 1:
The patent implements dynamic voltage switching capability in the ferroelectric capacitor, allowing it to operate in two modes: high voltage mode for non-volatile storage and low voltage mode for volatile operations. This dynamic adaptability enables the system to switch between retention-optimized and speed-optimized states, resolving the contradiction between data retention time and read/write speed.
3Adaptability or versatility
If plate line is added to enable ferroelectric memory operation, then memory functionality is improved, but cell size increases
Solution Approach 1:
The patent merges the plate line functionality with existing word lines or bit lines in the memory array. By combining the plate line's voltage switching function with existing signal lines, the patent eliminates the need for separate dedicated plate lines, thus maintaining full ferroelectric memory operation capability while reducing the overall memory cell area.
Solution Approach 2:
The patent makes existing memory lines multi-functional by having them serve both as word lines/bit lines and as plate lines for the ferroelectric capacitors. This universal usage of signal lines eliminates the need for additional dedicated plate lines, thereby maintaining memory functionality while reducing cell size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FeSRAM cell achieves improved endurance and faster read/write speeds without the need for frequent data refresh and eliminates the requirement for a separate decoder, resulting in a compact memory solution.
Implementation Method 1
Memory circuits using ferroelectric materials (e.g., lead zirconate Titanate (PZT)) have been proposed
Data Source
AI summary
A ferroelectric static random access memory (FeSRAM) cell includes (a) first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals; (b) first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and (c) first, second, third and fourth ferroelectric capacitors, wherein the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.