Ferroelectric Memory Cell Size Reduction via Shared Diffusion Layers
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices, such as those using ferroelectric gate transistors, face challenges in reducing memory cell size effectively.
Innovation Solution
The proposed storage device configuration includes a first and second transistor, each with a diffusion layer and a gate, along with first, second, and third switch transistors, which are selectively turned on to couple signal lines and diffusion layers, allowing for a reduced cell size by configuring each memory cell with 2.5 transistors instead of the traditional 3, utilizing ferroelectric gate transistors to store threshold states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional memory cell configuration with 3 transistors is used, then data storage function is ensured, but cell size cannot be reduced further
Solution Approach 1:
The patent merges the functions of multiple transistors by sharing diffusion layers between transistors. Specifically, the first diffusion layer is shared between the first transistor and second transistor, and the second diffusion layer is shared between the second transistor and third transistor. This merging of components reduces the total transistor count from 3 to 2.5 per memory cell while maintaining data storage functionality through selective coupling via switch transistors.
Solution Approach 2:
The diffusion layers serve multiple functions: they act as both source/drain regions for different transistors and as storage nodes for threshold state information. The first diffusion layer stores threshold state for the first transistor, while the second diffusion layer stores threshold state for the second transistor. This multi-functionality allows reduction in cell size without sacrificing storage capability.
2Area of moving object
If cell size is reduced, then storage density increases, but risk of data disturbance during programming and erasing increases
Solution Approach 1:
The patent segments the programming and erasing operations by using separate switch transistors (first, second, and third switch transistors) to control coupling between diffusion layers and signal lines. This segmentation allows selective activation of specific transistors during programming vs. erasing operations, preventing unwanted charge injection and data disturbance in adjacent cells, even when cell size is reduced.
Solution Approach 2:
The switch transistors act as intermediaries between the diffusion layers and signal lines. During programming, the first and second switch transistors couple the first and second diffusion layers to their respective signal lines. During erasing, the third switch transistor couples the second diffusion layer to the second signal line. This intermediary control mechanism ensures reliable data operations without disturbing adjacent cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the physical size of memory cells and minimizes the risk of data disturbance during programming and erasing operations, enabling efficient random access while maintaining data integrity.
Implementation Method 1
a ferroelectric gate transistor that makes it possible to store information using characteristics of spontaneous polarization of a ferroelectric substance
Data Source
AI summary
A storage device according to the disclosure includes a first transistor and a second transistor each including a first diffusion layer, a second diffusion layer, and a gate, and that are each able to store a threshold state, a first signal line, a second signal line, a first switch transistor that is turned on and couples the first signal line and the first diffusion layer of the first transistor, a second switch transistor that is turned on and couples the second diffusion layer of the first transistor and the first diffusion layer of the second transistor, and a third switch transistor that is turned on and couples the second diffusion layer of the second transistor and the second signal line.