3D Ferroelectric Memory Channel Structure Integration
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Solution Overview
Problem
The integration of two-dimensional memory devices is limited by the need for expensive equipment and limited chip die area, necessitating a shift towards three-dimensional memory devices with enhanced integration capabilities.
Innovation Solution
An integrated circuit device with a semiconductor substrate featuring conductive lines, insulating layers, and a channel structure that includes a core insulating layer, channel layer, gate insulating layer, and a ferroelectric layer on the outer walls of the gate insulating layer, which alternates with a high-k pattern, enabling efficient vertical memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional memory device integration is increased, then chip area utilization improves, but manufacturing cost increases due to expensive fine pattern equipment and chip die area limitations
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional structure by forming vertical channel structures that extend through multiple insulating layers and conductive lines. The channel structure includes a core insulating layer, channel layer, gate insulating layer, and ferroelectric layer stacked vertically, enabling higher integration without requiring additional chip area or expensive fine pattern equipment
2Productivity
If three-dimensional memory structure is implemented, then integration capability improves, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is divided into repeating modular units consisting of conductive lines, insulating layers, and channel structures. Each unit follows the same pattern of alternating conductive and insulating layers with vertically extending channel structures, simplifying the manufacturing process despite the three-dimensional configuration
Solution Approach 2:
The channel structure employs composite material layers including core insulating layer, channel layer, gate insulating layer, and ferroelectric layer. Each layer serves a specific function and the combination enables the three-dimensional structure to achieve high integration while maintaining manageable complexity through material property optimization
3Reliability
If ferroelectric layer is added to channel structure, then retention characteristics improve, but manufacturing process complexity increases
Solution Approach 1:
The ferroelectric layer is integrated into the existing channel structure formation process rather than being added as a separate subsequent step. The channel structure is formed to include the ferroelectric layer as an inherent component, merging the ferroelectric functionality with the standard memory cell structure fabrication
Solution Approach 2:
The patent utilizes the ferroelectric properties of the material layer to provide retention characteristics. By selecting materials with appropriate ferroelectric parameters and controlling their thickness and composition during formation, the device achieves improved data retention without fundamentally changing the manufacturing process flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory device integration, reduces working voltage, and improves retention characteristics and product reliability by utilizing remanent polarization to prevent electron or hole loss, thus overcoming the limitations of two-dimensional integration.
Implementation Method 1
utilizing remanent polarization to prevent electron or hole loss
Implementation Method 2
a gate insulating layer on an outer wall of the channel layer
Data Source
AI summary
An integrated circuit device includes a semiconductor substrate; a plurality of conductive lines extending on the semiconductor substrate in a horizontal direction and overlapping each other in a vertical direction; a plurality of insulating layers between pairs of conductive lines of the plurality of conductive lines and extending in the horizontal direction; and a channel structure passing through the plurality of conductive lines and the plurality of insulating layers, wherein the channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, a gate insulating layer on an outer wall of the channel layer, and a ferroelectric layer on an outer wall of the gate insulating layer.