Ferroelectric Memory Cell Layout With a Common Source Plate
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Solution Overview
Problem
The integration of semiconductor devices is limited by the resolution of pattern formation technologies, making it challenging to achieve higher integration and finer patterns, particularly in three-dimensional designs where cell arrangement is critical for performance and cost-effectiveness.
Innovation Solution
A semiconductor device design incorporating a substrate with a ferroelectric layer, conductive pillars, and an isolation layer, where the ferroelectric layer is positioned between conductive pillars and the common source plate, enhancing the arrangement of memory cells and increasing process efficiency by allowing for a common source plate without individual common source lines, thereby improving integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor devices are designed to increase integration density, then integration density is improved, but device complexity increases
Solution Approach 1:
The device is divided into multiple functional layers including bit lines, source lines, word lines, and memory cells arranged in a three-dimensional configuration. Each layer performs a specific function, allowing complex functionality to be achieved through modular segmentation rather than a monolithic structure.
Solution Approach 2:
The patent transitions from two-dimensional planar arrangement to three-dimensional stacking of memory cells, bit lines, and source lines. This vertical stacking in the third dimension enables higher integration density without proportionally increasing the footprint area, resolving the contradiction between density and complexity.
2Manufacturing precision
If pattern formation resolution is decreased to achieve finer patterns, then manufacturing precision is improved, but process capability deteriorates due to resolution limitations
Solution Approach 1:
The manufacturing process is divided into sequential steps: forming bit lines first, then source lines, followed by word lines and memory cells. This segmentation allows each component to be formed with optimized process parameters rather than requiring all features to be formed in a single high-resolution step.
Solution Approach 2:
Bit lines and source lines are formed in advance before the memory cells are created. This preliminary formation of interconnect structures establishes the foundation for subsequent cell formation, allowing the process to progress from simpler to more complex features and avoiding the need for ultra-fine patterning throughout the entire process.
3Device complexity
If common source plate is used without individual common source lines, then device complexity is reduced, but electrical connection reliability may worsen
Solution Approach 1:
Multiple source lines are merged into a single common source plate that extends beneath multiple memory cell strings. This consolidation reduces the total number of source line structures and simplifies the interconnect architecture while maintaining electrical connection to all necessary memory cells through the shared plate.
Solution Approach 2:
The common source plate serves multiple functions simultaneously: it acts as the source electrode for multiple memory cell strings, provides a reference potential plane, and enables simplified routing. This multi-functionality compensates for the potential reliability concerns by creating a robust, shared connection structure.
Data Source
AI summary
Provided is a semiconductor device. The semiconductor device includes a substrate; a first interlayer insulating layer, on the substrate, comprising a first interconnection; a common source plate on the first interlayer insulating layer; a conductive layer extending in a first direction on the common source plate; a ferroelectric layer on one sidewall of the conductive layer; a channel layer on the ferroelectric layer; a first conductive pillar, on the channel layer, penetrating the common source plate and being connected to the first interconnection; and a second conductive pillar, on the channel layer, spaced apart from the first conductive pillar in the first direction and connected to the common source plate, the ferroelectric layer and the channel layer between the common source plate and the first conductive pillar.