Ferroelectric Memory Gate with Control Electrode for Read Stability
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Solution Overview
Problem
Conventional semiconductor devices with ferroelectric memories face reliability issues during reading operations due to changes in the polarization state of the ferroelectric film when a voltage is applied between the threshold voltages of the writing and erasing states, leading to potential errors in data retrieval.
Innovation Solution
The semiconductor device incorporates a control gate electrode positioned between the memory gate electrode and the drain region, allowing for a voltage application to the control gate electrode and drain region that prevents bias to the memory gate electrode during reading, thereby maintaining the polarization state and enhancing reliability. Additionally, the ferroelectric film is formed with a length smaller than the dielectric film, allowing for effective electric field application and strong polarization, which improves hysteresis characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a voltage is applied to the gate electrode during reading operation to read data, then the reading operation can be performed, but the polarization state of the ferroelectric film may change, leading to reliability issues
Solution Approach 1:
The gate electrode is divided into two separate electrodes: a memory gate electrode that controls the ferroelectric film polarization, and a control gate electrode that applies voltage during reading operations. This segmentation allows the control gate to provide read voltage without causing unwanted polarization changes in the ferroelectric film, thus maintaining reliability while enabling reading operations.
Solution Approach 2:
A control gate electrode is introduced as an intermediary element between the memory gate electrode and the drain region. This control gate acts as a mediator that enables reading operations by applying voltage to the drain region without directly affecting the memory gate electrode or causing polarization state changes in the ferroelectric film.
2Productivity
If the memory gate electrode length is scaled down to improve device density, then more devices can be integrated, but the hysteresis characteristics and reliability deteriorate
Solution Approach 1:
The invention introduces a vertical dimension by adding a control gate electrode positioned between the memory gate electrode and the drain region. This vertical stacking approach allows the memory gate electrode to be shortened for higher density while the control gate provides the necessary electric field control in the vertical direction to maintain hysteresis characteristics and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the risk of polarization state changes during reading operations, increases the reliability of the semiconductor device, and enhances hysteresis characteristics by effectively applying the electric field to the ferroelectric film, leading to improved performance, especially when the memory gate electrode length is scaled down.
Implementation Method 1
a ferroelectric film formed on one part of the conductive film; a memory gate electrode formed on the ferroelectric film
Implementation Method 2
a first dielectric film formed on the first region of the semiconductor substrate; a conductive film formed on the first dielectric film
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first dielectric film, a conductive film, at least one ferroelectric film, a second dielectric film, a memory gate electrode, a third dielectric film and a control gate electrode. The semiconductor substrate includes a source region and a drain region. The semiconductor substrate includes a first region and a second region between the source region and the drain region. The first dielectric film is formed on the first region. The conductive film is formed on the first dielectric film. The at least one ferroelectric film is formed on one hart of the conductive film. The second dielectric film is formed on the other part of the conductive film. The memory gate electrode is formed on the ferroelectric film. The third dielectric film is formed on the second region. The control gate electrode is formed on the third dielectric film.