Ferroelectric Memory Cell Structure for Low-Power Dense Arrays
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving low power consumption, high reliability, small area occupation, and high memory capacity, particularly in next-generation ferroelectric memory systems using materials like hafnium oxide.
Innovation Solution
A semiconductor device with a memory cell comprising a transistor and a ferroelectric capacitor, where the transistor includes an oxide semiconductor channel with indium and zinc, and the ferroelectric material contains nitrogen and elements like aluminum, gallium, and hafnium, optimized for low power consumption and high memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional memory structures are used, then device complexity is reduced, but power consumption increases and memory capacity decreases
Solution Approach 1:
The patent merges the word line and bit line functions into a single shared line structure. The memory cell uses a single transistor where the gate serves as the word line and the drain serves as the bit line, eliminating the need for separate word and bit lines. This integration reduces the number of components and interconnections, thereby reducing device complexity while maintaining low power consumption through the ferroelectric capacitor's non-volatile storage capability.
Solution Approach 2:
The single transistor in the memory cell performs multiple functions: the gate terminal serves as the word line for selecting memory cells, the drain terminal serves as the bit line for data input/output, and the ferroelectric capacitor provides non-volatile storage. This multi-functionality reduces the number of dedicated components needed, simplifying the overall device structure while enabling low power operation.
2Quantity of substance
If memory capacity is increased, then area occupation increases, but power consumption and reliability are affected
Solution Approach 1:
The patent implements a nested structure where multiple memory cells can be stacked vertically or arranged in a compact configuration. The shared line structure allows memory cells to be nested along the channel length direction, with multiple cells sharing the same word line and bit line infrastructure. This nesting approach increases memory capacity without proportionally increasing the planar area occupation.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional structure by extending the memory cell array in the vertical direction or by stacking multiple layers. The shared line structure enables this dimensional expansion, allowing memory capacity to scale with volume rather than just area, thereby increasing capacity without proportionally increasing footprint area.
3Use of energy by moving object
If ferroelectric material is used, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the ferroelectric material parameters, specifically using hafnium oxide with controlled oxygen vacancy concentration and crystal phase composition. By adjusting the material parameters such as composition ratio, thickness, and doping level, the ferroelectric properties are enhanced while maintaining compatibility with standard semiconductor manufacturing processes, thereby reducing the precision requirements for fabrication.
Solution Approach 2:
The patent employs composite material structures, such as stacking multiple ferroelectric layers with different compositions or combining ferroelectric hafnium oxide with other functional materials. This composite approach allows the system to achieve the desired ferroelectric performance while being more tolerant of manufacturing variations, as the composite structure can compensate for deviations in individual layer properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor device with low power consumption, high reliability, and high memory capacity, enabling efficient data storage while occupying a smaller area, suitable for next-generation memory systems.
Implementation Method 1
a capacitor including a ferroelectric
Implementation Method 2
a transistor and a capacitor including a ferroelectric, where a gate of the transistor is electrically connected to the first wiring; one of a source and a drain of the transistor is electrically connected to the second wiring
Data Source
AI summary
A novel semiconductor device is provided. The semiconductor device includes a memory cell including a transistor and a capacitor that includes a ferroelectric; a word line; a bit line; and a plate line. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor. The other electrode of the capacitor is electrically connected to the plate line. The semiconductor device has a function of supplying a potential that controls an on state or an off state of the transistor to the word line, a function of supplying a first potential or a second potential to the bit line, and a function of supplying a third potential, a fourth potential, or a fifth potential to the plate line.