Ferroelectric Memory Cell Layout for Disturb Effect Control
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Solution Overview
Problem
Existing ferroelectric memory devices face challenges in reducing disturb effects during operation, particularly in ferroelectric memory transistors, due to the lack of effective control over the common channel shared by select and control gate transistors.
Innovation Solution
The integration of a select gate transistor with a longer select gate electrode that controls a portion of the common channel adjacent to the source region, reducing disturb effects by minimizing interference during device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a select gate transistor shares a common channel with a ferroelectric memory transistor, then device complexity is reduced and manufacturing is simplified, but disturb effects increase during operation due to lack of independent channel control
Solution Approach 1:
The common channel is segmented into two distinct regions: a first channel region under the select gate electrode and a second channel region under the control gate electrode. This segmentation allows independent control of each transistor's channel, enabling the select gate transistor to control access to the channel while the control gate electrode controls the ferroelectric memory transistor, thereby reducing disturb effects during read and write operations.
2Reliability
If the select gate electrode length is increased to improve control over the common channel, then disturb effects are reduced, but device area increases
Solution Approach 1:
The select gate electrode is designed with a length that specifically covers the first channel region adjacent to the source region, providing localized control where it is most needed to prevent disturb effects. The electrode does not extend unnecessarily over the second channel region, optimizing the balance between control effectiveness and area utilization.
3Reliability
If the select gate transistor controls the common channel adjacent to the source region, then interference during operation is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The first and second channel regions are merged into a continuous common channel structure, eliminating the need for separate channel formation processes. This merging simplifies manufacturing while maintaining the ability to independently control each region through their respective gate electrodes, as the channel continuity ensures proper electrical connection while the gate electrodes provide independent control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces disturb effects in ferroelectric memory transistors by controlling the common channel, enhancing the reliability and performance of the memory device.
Implementation Method 1
A ferroelectric material refers to a material that displays spontaneous polarization of electrical charges in the absence of an applied electric field. The net polarization P of electrical charges within the ferroelectric material is non-zero in the minimum energy state.
Implementation Method 2
Polarization P of a ferroelectric material as a function of an applied voltage V thereacross displays hysteresis. The product of the remanent polarization and the coercive field of a ferroelectric material is a metric for characterizing effectiveness of the ferroelectric material.
Implementation Method 3
The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring electrical current passing through a semiconductor channel provided adjacent to the ferroelectric material in a field effect transistor ferroelectric memory device.
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
A memory cell includes a ferroelectric memory transistor, and a select gate transistor which shares a common semiconductor channel, a common source region and a common drain region with the ferroelectric memory transistor. The select gate transistor controls access between the common source region and the common semiconductor channel.