Ferroelectric Memory Device Erase Disturb Control
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Solution Overview
Problem
Ferroelectric memory devices face challenges in efficiently performing erase and write operations without causing disturb, which affects data integrity and reliability, particularly in erase sequences performed in units of one layer.
Innovation Solution
The memory device employs a specific voltage control method during erase and write sequences, applying distinct voltage levels to select and non-select word lines, bit lines, and source lines to manage the threshold voltage of ferroelectric transistors, preventing erase disturb and ensuring accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase sequence is performed in units of one layer, then erase operation efficiency is improved, but erase disturb occurs affecting data integrity
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their selection status. Non-selected word lines receive a first voltage level (e.g., 0V or negative voltage) while selected word lines receive a second voltage level (e.g., positive voltage). This local differentiation prevents erase disturb in non-selected memory cells while enabling efficient erase operation in selected cells, thus resolving the contradiction between erase efficiency and data integrity.
Solution Approach 2:
The patent changes the voltage parameter applied to word lines during erase operations. By dynamically adjusting voltage levels based on whether word lines are selected or non-selected, the system achieves both high erase efficiency and maintains data integrity. The voltage parameter transformation from a uniform approach to a differentiated approach resolves the technical contradiction.
2Productivity
If voltage levels are increased to improve write speed, then productivity is improved, but disturb to non-selected cells increases
Solution Approach 1:
The patent implements local quality control by applying different voltage levels to selected and non-selected word lines. During write operations, selected word lines receive higher voltage levels to enable fast programming, while non-selected word lines receive lower or zero voltage to prevent disturb. This spatial differentiation resolves the contradiction between write speed and disturbance prevention.
Solution Approach 2:
The patent applies preliminary anti-action by pre-setting voltage levels on non-selected word lines to counteract potential disturb effects before they occur. By applying appropriate voltage levels (e.g., 0V or negative voltage) to non-selected word lines during write operations, the system prevents unwanted changes in non-selected memory cells while maintaining high write speed in selected cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces errors caused by erase disturb, enhances data reliability, and maintains the integrity of stored data by carefully managing voltage levels during operational sequences.
Implementation Method 1
a memory device that stores data by utilizing the polarization characteristics of a ferroelectric material
Data Source
AI summary
According to one embodiment, a device includes: first and third transistors coupled to a bit line; first cells coupled to the first transistor; second cells coupled to the third transistor; a first line coupled to a gate of the first transistor; a second line coupled to a gate of the third transistor; word lines coupled to gates of the first and second cells; and a circuit. Each of the first and second cells includes a ferroelectric transistor. In the erase sequence, the circuit applies a first voltage having a positive value to the bit line, applies a second voltage higher than the first voltage to the first and second lines, applies a third voltage higher than the first voltage to non-selected word lines, and applies a fourth voltage lower than the first voltage to a selected word line.