Ferroelectric Memory Cell Structure for Electric Field Relief
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Solution Overview
Problem
Existing semiconductor devices with ferroelectric layers face endurance issues due to excessive electric field concentration on non-ferroelectric layers, leading to deterioration of electrical properties and reduced cell integration density.
Innovation Solution
The semiconductor device design includes a configuration where the overlap area between the floating electrode layer and the non-ferroelectric layer is greater than the overlap area between the ferroelectric layer and the word line, controlling the ratio of capacitances to reduce electric field concentration on the non-ferroelectric layer and enhance the endurance of the device, while maintaining a three-dimensional structure for improved cell integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the overlap area between ferroelectric layer and word line is increased to improve capacitance, then the electric field concentration on non-ferroelectric layer increases, but this leads to deterioration of electrical properties and reduced endurance
Solution Approach 1:
The patent introduces a floating electrode layer positioned between the non-ferroelectric layer and the ferroelectric layer, creating a new spatial dimension in the capacitor structure. This floating electrode divides the original capacitor into two series capacitors, redistributing the electric field in the vertical dimension and reducing concentration on the non-ferroelectric layer while maintaining overall capacitance.
Solution Approach 2:
The floating electrode layer acts as an intermediary element between the non-ferroelectric layer and the ferroelectric layer. It mediates the electric field distribution by providing an additional interface, thereby reducing the direct electric field concentration on the non-ferroelectric layer and preventing its deterioration.
2Reliability
If the overlap area between floating electrode layer and non-ferroelectric layer is increased to reduce electric field concentration, then the capacitance ratio changes, but this may affect the overall device performance
Solution Approach 1:
The patent optimizes the overlap areas between different layers by adjusting geometric parameters. Specifically, the overlap area between the floating electrode layer and non-ferroelectric layer is made larger than the overlap area between the ferroelectric layer and word line, changing the capacitance ratio to favor reduced electric field concentration while maintaining acceptable overall capacitance.
3Reliability
If the device structure is made more complex with additional floating electrode layer, then the electric field distribution is improved, but the manufacturing process becomes more difficult
Solution Approach 1:
The capacitor structure is segmented into two separate capacitor regions by introducing the floating electrode layer. This segmentation allows independent optimization of each capacitor's characteristics and simplifies the control of electric field distribution, making the manufacturing process more manageable despite the increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively alleviates the deterioration of electrical properties by reducing electric field concentration on the non-ferroelectric layer, thereby improving the endurance and integration density of the semiconductor device.
Implementation Method 1
a ferroelectric material refers to a material having spontaneous electrical polarization in a state where no external electric field is applied. In addition, the electrical polarization may exhibit a hysteresis behavior when an external electric field is applied. Accordingly, if the external electric field applied to the ferroelectric material is controlled, polarizations having various magnitudes and orientations according to the hysteresis behavior may be reversibly implemented in the ferroelectric material. Meanwhile, the polarization is non-volatilely stored in the ferroelectric material after the external electric field is removed
Implementation Method 2
there has been disclosed a capacitor device including a dielectric structure DS between a first node N1 and a second node N2. The dielectric structure DS may include a non-ferroelectric layer DE and a ferroelectric layer FE, which are connected in series to each other
Data Source
AI summary
A semiconductor device according to an embodiment includes a substrate, a bit line and a source line extending in a vertical direction substantially perpendicular to a surface of the substrate, a semiconductor layer disposed between the source line and the bit line on a plane substantially parallel to the surface of the substrate, a non-ferroelectric layer pattern disposed on the semiconductor layer, a floating electrode layer pattern disposed on the non-ferroelectric layer pattern, a ferroelectric layer pattern disposed on the floating electrode layer pattern, and a word line disposed on the ferroelectric layer pattern. An overlap area between the floating electrode layer pattern and the non-ferroelectric layer pattern in the vertical direction is greater than an overlap area between the ferroelectric layer pattern and the word line in the vertical direction.